2021-07-15 19:28:19 +08:00
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|
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//! # Dual IIR
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//!
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//! The Dual IIR application exposes two configurable channels. Stabilizer samples input at a fixed
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|
//! rate, digitally filters the data, and then generates filtered output signals on the respective
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//! channel outputs.
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//!
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//! ## Features
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//! * Two indpenendent channels
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//! * up to 800 kHz rate, timed sampling
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//! * Run-time filter configuration
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//! * Input/Output data streaming
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//! * Down to 2 µs latency
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//! * f32 IIR math
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//! * Generic biquad (second order) IIR filter
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//! * Anti-windup
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//! * Derivative kick avoidance
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//!
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//! ## Settings
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|
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//! Refer to the [Settings] structure for documentation of run-time configurable settings for this
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//! application.
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//!
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//! ## Telemetry
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//! Refer to [Telemetry] for information about telemetry reported by this application.
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//!
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//! ## Livestreaming
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//! This application streams raw ADC and DAC data over UDP. Refer to
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|
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//! [stabilizer::net::data_stream](../stabilizer/net/data_stream/index.html) for more information.
|
2021-01-20 20:43:34 +08:00
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|
|
#![deny(warnings)]
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|
|
|
#![no_std]
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|
|
#![no_main]
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|
2021-07-19 19:01:31 +08:00
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|
use core::{
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|
|
|
convert::TryInto,
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|
|
|
sync::atomic::{fence, Ordering},
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|
|
|
};
|
2021-01-28 01:15:35 +08:00
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|
|
|
2021-06-24 19:03:54 +08:00
|
|
|
use mutex_trait::prelude::*;
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|
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|
2021-01-20 20:43:34 +08:00
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|
use dsp::iir;
|
2021-05-17 19:01:45 +08:00
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use stabilizer::{
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hardware::{
|
2021-06-04 23:02:01 +08:00
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|
self,
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|
adc::{Adc0Input, Adc1Input, AdcCode},
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afe::Gain,
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dac::{Dac0Output, Dac1Output, DacCode},
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2021-07-22 20:45:58 +08:00
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|
design_parameters::SAMPLE_BUFFER_SIZE,
|
2021-06-04 23:02:01 +08:00
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|
|
embedded_hal::digital::v2::InputPin,
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|
|
hal,
|
2021-06-28 19:40:59 +08:00
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signal_generator::{self, SignalGenerator},
|
2021-06-04 23:02:01 +08:00
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|
system_timer::SystemTimer,
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DigitalInput0, DigitalInput1, AFE0, AFE1,
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|
},
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net::{
|
2021-07-23 21:08:07 +08:00
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|
data_stream::{FrameGenerator, StreamFormat, StreamTarget},
|
2021-06-04 23:02:01 +08:00
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|
miniconf::Miniconf,
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|
|
serde::Deserialize,
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|
|
telemetry::{Telemetry, TelemetryBuffer},
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NetworkState, NetworkUsers,
|
2021-05-17 19:01:45 +08:00
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},
|
2021-05-17 18:43:04 +08:00
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|
|
};
|
2021-03-18 03:16:13 +08:00
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|
2021-02-02 00:18:10 +08:00
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|
const SCALE: f32 = i16::MAX as _;
|
2021-01-20 20:43:34 +08:00
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// The number of cascaded IIR biquads per channel. Select 1 or 2!
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|
|
const IIR_CASCADE_LENGTH: usize = 1;
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|
2021-04-14 22:09:54 +08:00
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|
|
#[derive(Clone, Copy, Debug, Deserialize, Miniconf)]
|
2021-01-28 01:15:35 +08:00
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pub struct Settings {
|
2021-07-15 19:28:19 +08:00
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/// Configure the Analog Front End (AFE) gain.
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///
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/// # Path
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/// `afe/<n>`
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///
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|
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/// * <n> specifies which channel to configure. <n> := [0, 1]
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|
///
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/// # Value
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/// Any of the variants of [Gain] enclosed in double quotes.
|
2021-06-04 23:02:01 +08:00
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|
afe: [Gain; 2],
|
2021-07-15 19:28:19 +08:00
|
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/// Configure the IIR filter parameters.
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///
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/// # Path
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/// `iir_ch/<n>/<m>`
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|
///
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|
|
/// * <n> specifies which channel to configure. <n> := [0, 1]
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|
|
/// * <m> specifies which cascade to configure. <m> := [0, 1], depending on [IIR_CASCADE_LENGTH]
|
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|
|
///
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|
|
/// # Value
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|
|
/// See [iir::IIR#miniconf]
|
2021-02-17 19:59:24 +08:00
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|
|
iir_ch: [[iir::IIR; IIR_CASCADE_LENGTH]; 2],
|
2021-07-15 19:28:19 +08:00
|
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|
|
/// Specified true if DI1 should be used as a "hold" input.
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|
|
///
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|
|
|
/// # Path
|
|
|
|
/// `allow_hold`
|
|
|
|
///
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|
|
|
/// # Value
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|
|
|
/// "true" or "false"
|
2021-04-14 22:09:54 +08:00
|
|
|
allow_hold: bool,
|
2021-07-15 19:28:19 +08:00
|
|
|
|
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|
|
/// Specified true if "hold" should be forced regardless of DI1 state and hold allowance.
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|
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|
///
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|
|
/// # Path
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|
|
|
/// `force_hold`
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|
|
|
///
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|
|
/// # Value
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|
|
/// "true" or "false"
|
2021-04-14 22:09:54 +08:00
|
|
|
force_hold: bool,
|
2021-07-15 19:28:19 +08:00
|
|
|
|
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|
|
/// Specifies the telemetry output period in seconds.
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|
|
///
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|
|
/// # Path
|
|
|
|
/// `telemetry_period`
|
|
|
|
///
|
|
|
|
/// # Value
|
|
|
|
/// Any non-zero value less than 65536.
|
2021-05-07 19:02:14 +08:00
|
|
|
telemetry_period: u16,
|
2021-07-15 19:28:19 +08:00
|
|
|
|
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|
|
/// Specifies the target for data livestreaming.
|
|
|
|
///
|
|
|
|
/// # Path
|
|
|
|
/// `stream_target`
|
|
|
|
///
|
|
|
|
/// # Value
|
|
|
|
/// See [StreamTarget#miniconf]
|
2021-06-09 21:25:59 +08:00
|
|
|
stream_target: StreamTarget,
|
2021-07-19 18:46:06 +08:00
|
|
|
|
|
|
|
/// Specifies the config for signal generators to add on to DAC0/DAC1 outputs.
|
|
|
|
///
|
|
|
|
/// # Path
|
|
|
|
/// `signal_generator/<n>`
|
|
|
|
///
|
|
|
|
/// * <n> specifies which channel to configure. <n> := [0, 1]
|
|
|
|
///
|
|
|
|
/// # Value
|
|
|
|
/// See [signal_generator::BasicConfig#miniconf]
|
2021-06-29 19:23:42 +08:00
|
|
|
signal_generator: [signal_generator::BasicConfig; 2],
|
2021-01-28 01:15:35 +08:00
|
|
|
}
|
|
|
|
|
2021-02-17 19:59:24 +08:00
|
|
|
impl Default for Settings {
|
|
|
|
fn default() -> Self {
|
|
|
|
Self {
|
2021-04-28 22:27:59 +08:00
|
|
|
// Analog frontend programmable gain amplifier gains (G1, G2, G5, G10)
|
2021-06-04 23:02:01 +08:00
|
|
|
afe: [Gain::G1, Gain::G1],
|
2021-04-28 22:27:59 +08:00
|
|
|
// IIR filter tap gains are an array `[b0, b1, b2, a1, a2]` such that the
|
|
|
|
// new output is computed as `y0 = a1*y1 + a2*y2 + b0*x0 + b1*x1 + b2*x2`.
|
|
|
|
// The array is `iir_state[channel-index][cascade-index][coeff-index]`.
|
|
|
|
// The IIR coefficients can be mapped to other transfer function
|
|
|
|
// representations, for example as described in https://arxiv.org/abs/1508.06319
|
2021-02-17 19:59:24 +08:00
|
|
|
iir_ch: [[iir::IIR::new(1., -SCALE, SCALE); IIR_CASCADE_LENGTH]; 2],
|
2021-04-28 22:27:59 +08:00
|
|
|
// Permit the DI1 digital input to suppress filter output updates.
|
2021-04-14 22:09:54 +08:00
|
|
|
allow_hold: false,
|
2021-04-28 22:27:59 +08:00
|
|
|
// Force suppress filter output updates.
|
2021-04-14 22:09:54 +08:00
|
|
|
force_hold: false,
|
2021-05-10 17:10:26 +08:00
|
|
|
// The default telemetry period in seconds.
|
2021-05-07 19:02:14 +08:00
|
|
|
telemetry_period: 10,
|
2021-06-09 21:25:59 +08:00
|
|
|
|
2021-06-29 19:23:42 +08:00
|
|
|
signal_generator: [signal_generator::BasicConfig::default(); 2],
|
2021-06-28 19:16:54 +08:00
|
|
|
|
2021-06-09 21:25:59 +08:00
|
|
|
stream_target: StreamTarget::default(),
|
2021-02-17 19:59:24 +08:00
|
|
|
}
|
2021-01-28 01:15:35 +08:00
|
|
|
}
|
2021-01-26 21:28:06 +08:00
|
|
|
}
|
|
|
|
|
2021-06-04 23:02:01 +08:00
|
|
|
#[rtic::app(device = stabilizer::hardware::hal::stm32, peripherals = true, monotonic = stabilizer::hardware::system_timer::SystemTimer)]
|
2021-01-20 20:43:34 +08:00
|
|
|
const APP: () = {
|
|
|
|
struct Resources {
|
|
|
|
afes: (AFE0, AFE1),
|
2021-04-15 21:43:40 +08:00
|
|
|
digital_inputs: (DigitalInput0, DigitalInput1),
|
2021-01-20 20:43:34 +08:00
|
|
|
adcs: (Adc0Input, Adc1Input),
|
|
|
|
dacs: (Dac0Output, Dac1Output),
|
2021-05-05 22:16:54 +08:00
|
|
|
network: NetworkUsers<Settings, Telemetry>,
|
2021-07-22 20:45:58 +08:00
|
|
|
generator: FrameGenerator,
|
2021-06-29 19:23:42 +08:00
|
|
|
signal_generator: [SignalGenerator; 2],
|
2021-05-05 20:42:17 +08:00
|
|
|
|
2021-04-15 20:40:47 +08:00
|
|
|
settings: Settings,
|
2021-05-05 21:39:33 +08:00
|
|
|
telemetry: TelemetryBuffer,
|
2021-01-20 20:43:34 +08:00
|
|
|
|
2021-02-17 19:59:24 +08:00
|
|
|
#[init([[[0.; 5]; IIR_CASCADE_LENGTH]; 2])]
|
2021-02-01 19:22:50 +08:00
|
|
|
iir_state: [[iir::Vec5; IIR_CASCADE_LENGTH]; 2],
|
2021-01-20 20:43:34 +08:00
|
|
|
}
|
|
|
|
|
2021-05-31 20:28:57 +08:00
|
|
|
#[init(spawn=[telemetry, settings_update, ethernet_link])]
|
2021-01-20 20:43:34 +08:00
|
|
|
fn init(c: init::Context) -> init::LateResources {
|
|
|
|
// Configure the microcontroller
|
2021-06-04 23:02:01 +08:00
|
|
|
let (mut stabilizer, _pounder) =
|
|
|
|
hardware::setup::setup(c.core, c.device);
|
2021-01-20 20:43:34 +08:00
|
|
|
|
2021-05-17 18:43:04 +08:00
|
|
|
let mut network = NetworkUsers::new(
|
2021-05-05 22:16:54 +08:00
|
|
|
stabilizer.net.stack,
|
|
|
|
stabilizer.net.phy,
|
|
|
|
stabilizer.cycle_counter,
|
|
|
|
env!("CARGO_BIN_NAME"),
|
|
|
|
stabilizer.net.mac_address,
|
|
|
|
);
|
2021-01-31 01:57:06 +08:00
|
|
|
|
2021-07-27 19:12:57 +08:00
|
|
|
let generator = network.configure_streaming(
|
|
|
|
StreamFormat::AdcDacData,
|
|
|
|
SAMPLE_BUFFER_SIZE as u8,
|
|
|
|
);
|
2021-05-17 18:43:04 +08:00
|
|
|
|
2021-04-14 22:09:54 +08:00
|
|
|
// Spawn a settings update for default settings.
|
|
|
|
c.spawn.settings_update().unwrap();
|
2021-04-15 21:43:40 +08:00
|
|
|
c.spawn.telemetry().unwrap();
|
2021-04-14 22:09:54 +08:00
|
|
|
|
2021-05-31 20:28:57 +08:00
|
|
|
// Spawn the ethernet link period check task.
|
|
|
|
c.spawn.ethernet_link().unwrap();
|
|
|
|
|
2021-01-20 20:43:34 +08:00
|
|
|
// Enable ADC/DAC events
|
|
|
|
stabilizer.adcs.0.start();
|
|
|
|
stabilizer.adcs.1.start();
|
|
|
|
stabilizer.dacs.0.start();
|
|
|
|
stabilizer.dacs.1.start();
|
|
|
|
|
|
|
|
// Start sampling ADCs.
|
2021-04-15 21:08:57 +08:00
|
|
|
stabilizer.adc_dac_timer.start();
|
2021-04-15 20:40:47 +08:00
|
|
|
|
2021-06-28 19:40:59 +08:00
|
|
|
let settings = Settings::default();
|
|
|
|
|
2021-01-20 20:43:34 +08:00
|
|
|
init::LateResources {
|
|
|
|
afes: stabilizer.afes,
|
|
|
|
adcs: stabilizer.adcs,
|
|
|
|
dacs: stabilizer.dacs,
|
2021-05-17 18:43:04 +08:00
|
|
|
generator,
|
2021-05-05 20:42:17 +08:00
|
|
|
network,
|
2021-04-15 21:43:40 +08:00
|
|
|
digital_inputs: stabilizer.digital_inputs,
|
2021-05-17 19:01:45 +08:00
|
|
|
telemetry: TelemetryBuffer::default(),
|
2021-06-28 19:40:59 +08:00
|
|
|
settings,
|
2021-06-29 19:23:42 +08:00
|
|
|
signal_generator: [
|
2021-07-19 19:01:31 +08:00
|
|
|
SignalGenerator::new(
|
|
|
|
settings.signal_generator[0].try_into().unwrap(),
|
|
|
|
),
|
|
|
|
SignalGenerator::new(
|
|
|
|
settings.signal_generator[1].try_into().unwrap(),
|
|
|
|
),
|
2021-06-29 19:23:42 +08:00
|
|
|
],
|
2021-01-20 20:43:34 +08:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
/// Main DSP processing routine for Stabilizer.
|
|
|
|
///
|
|
|
|
/// # Note
|
|
|
|
/// Processing time for the DSP application code is bounded by the following constraints:
|
|
|
|
///
|
|
|
|
/// DSP application code starts after the ADC has generated a batch of samples and must be
|
|
|
|
/// completed by the time the next batch of ADC samples has been acquired (plus the FIFO buffer
|
|
|
|
/// time). If this constraint is not met, firmware will panic due to an ADC input overrun.
|
|
|
|
///
|
|
|
|
/// The DSP application code must also fill out the next DAC output buffer in time such that the
|
|
|
|
/// DAC can switch to it when it has completed the current buffer. If this constraint is not met
|
|
|
|
/// it's possible that old DAC codes will be generated on the output and the output samples will
|
|
|
|
/// be delayed by 1 batch.
|
|
|
|
///
|
|
|
|
/// Because the ADC and DAC operate at the same rate, these two constraints actually implement
|
|
|
|
/// the same time bounds, meeting one also means the other is also met.
|
2021-06-28 19:40:59 +08:00
|
|
|
#[task(binds=DMA1_STR4, resources=[adcs, digital_inputs, dacs, iir_state, settings, signal_generator, telemetry, generator], priority=2)]
|
2021-03-29 02:32:50 +08:00
|
|
|
#[inline(never)]
|
|
|
|
#[link_section = ".itcm.process"]
|
2021-05-25 02:06:31 +08:00
|
|
|
fn process(mut c: process::Context) {
|
2021-05-25 04:41:22 +08:00
|
|
|
let process::Resources {
|
|
|
|
adcs: (ref mut adc0, ref mut adc1),
|
|
|
|
dacs: (ref mut dac0, ref mut dac1),
|
|
|
|
ref digital_inputs,
|
|
|
|
ref settings,
|
|
|
|
ref mut iir_state,
|
|
|
|
ref mut telemetry,
|
2021-06-09 18:52:13 +08:00
|
|
|
ref mut generator,
|
2021-06-28 19:40:59 +08:00
|
|
|
ref mut signal_generator,
|
2021-05-25 04:41:22 +08:00
|
|
|
} = c.resources;
|
2021-01-20 20:43:34 +08:00
|
|
|
|
2021-05-07 19:02:14 +08:00
|
|
|
let digital_inputs = [
|
2021-05-25 04:41:22 +08:00
|
|
|
digital_inputs.0.is_high().unwrap(),
|
|
|
|
digital_inputs.1.is_high().unwrap(),
|
2021-05-07 19:02:14 +08:00
|
|
|
];
|
2021-05-25 04:41:22 +08:00
|
|
|
telemetry.digital_inputs = digital_inputs;
|
|
|
|
|
|
|
|
let hold =
|
|
|
|
settings.force_hold || (digital_inputs[1] && settings.allow_hold);
|
|
|
|
|
2021-06-24 19:03:54 +08:00
|
|
|
(adc0, adc1, dac0, dac1).lock(|adc0, adc1, dac0, dac1| {
|
2021-05-25 18:05:19 +08:00
|
|
|
let adc_samples = [adc0, adc1];
|
|
|
|
let dac_samples = [dac0, dac1];
|
|
|
|
|
|
|
|
// Preserve instruction and data ordering w.r.t. DMA flag access.
|
|
|
|
fence(Ordering::SeqCst);
|
|
|
|
|
|
|
|
for channel in 0..adc_samples.len() {
|
2021-06-29 19:23:42 +08:00
|
|
|
adc_samples[channel]
|
|
|
|
.iter()
|
|
|
|
.zip(dac_samples[channel].iter_mut())
|
|
|
|
.zip(&mut signal_generator[channel])
|
|
|
|
.map(|((ai, di), signal)| {
|
|
|
|
let x = f32::from(*ai as i16);
|
|
|
|
let y = settings.iir_ch[channel]
|
2021-05-25 18:05:19 +08:00
|
|
|
.iter()
|
2021-06-29 19:23:42 +08:00
|
|
|
.zip(iir_state[channel].iter_mut())
|
|
|
|
.fold(x, |yi, (ch, state)| {
|
|
|
|
ch.update(state, yi, hold)
|
|
|
|
});
|
|
|
|
|
|
|
|
// Note(unsafe): The filter limits must ensure that the value is in range.
|
|
|
|
// The truncation introduces 1/2 LSB distortion.
|
|
|
|
let y: i16 = unsafe { y.to_int_unchecked() };
|
|
|
|
|
|
|
|
let y = y.saturating_add(signal);
|
2021-06-28 19:16:54 +08:00
|
|
|
|
2021-06-29 19:23:42 +08:00
|
|
|
// Convert to DAC code
|
|
|
|
*di = DacCode::from(y).0;
|
|
|
|
})
|
|
|
|
.last();
|
2021-01-20 20:43:34 +08:00
|
|
|
}
|
2021-04-15 20:40:47 +08:00
|
|
|
|
2021-06-09 18:46:56 +08:00
|
|
|
// Stream the data.
|
2021-07-26 18:24:36 +08:00
|
|
|
const N: usize = SAMPLE_BUFFER_SIZE * core::mem::size_of::<u16>();
|
|
|
|
generator.add::<_, { N * 4 }>(|buf| {
|
|
|
|
for (data, buf) in adc_samples
|
|
|
|
.iter()
|
|
|
|
.chain(dac_samples.iter())
|
|
|
|
.zip(buf.chunks_exact_mut(N))
|
|
|
|
{
|
2021-07-26 19:47:03 +08:00
|
|
|
assert_eq!(core::mem::size_of_val(*data), N);
|
2021-07-26 18:24:36 +08:00
|
|
|
let data = unsafe {
|
|
|
|
core::slice::from_raw_parts(
|
|
|
|
data.as_ptr() as *const u8,
|
|
|
|
N,
|
|
|
|
)
|
|
|
|
};
|
|
|
|
buf.copy_from_slice(data)
|
|
|
|
}
|
|
|
|
});
|
2021-05-17 18:43:04 +08:00
|
|
|
|
2021-05-25 18:05:19 +08:00
|
|
|
// Update telemetry measurements.
|
|
|
|
telemetry.adcs =
|
|
|
|
[AdcCode(adc_samples[0][0]), AdcCode(adc_samples[1][0])];
|
2021-04-15 20:40:47 +08:00
|
|
|
|
2021-05-25 18:05:19 +08:00
|
|
|
telemetry.dacs =
|
|
|
|
[DacCode(dac_samples[0][0]), DacCode(dac_samples[1][0])];
|
2021-04-15 21:43:40 +08:00
|
|
|
|
2021-05-25 18:05:19 +08:00
|
|
|
// Preserve instruction and data ordering w.r.t. DMA flag access.
|
|
|
|
fence(Ordering::SeqCst);
|
2021-05-25 02:06:31 +08:00
|
|
|
});
|
2021-01-20 20:43:34 +08:00
|
|
|
}
|
|
|
|
|
2021-05-05 20:42:17 +08:00
|
|
|
#[idle(resources=[network], spawn=[settings_update])]
|
2021-01-20 20:43:34 +08:00
|
|
|
fn idle(mut c: idle::Context) -> ! {
|
|
|
|
loop {
|
2021-05-05 22:46:53 +08:00
|
|
|
match c.resources.network.lock(|net| net.update()) {
|
2021-05-26 19:05:54 +08:00
|
|
|
NetworkState::SettingsChanged => {
|
|
|
|
c.spawn.settings_update().unwrap()
|
|
|
|
}
|
|
|
|
NetworkState::Updated => {}
|
2021-06-09 21:30:33 +08:00
|
|
|
NetworkState::NoChange => cortex_m::asm::wfi(),
|
2021-01-20 20:43:34 +08:00
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2021-06-28 19:40:59 +08:00
|
|
|
#[task(priority = 1, resources=[network, afes, settings, signal_generator])]
|
2021-02-17 19:59:24 +08:00
|
|
|
fn settings_update(mut c: settings_update::Context) {
|
|
|
|
// Update the IIR channels.
|
2021-05-26 23:56:44 +08:00
|
|
|
let settings = c.resources.network.miniconf.settings();
|
|
|
|
c.resources.settings.lock(|current| *current = *settings);
|
2021-04-15 20:40:47 +08:00
|
|
|
|
2021-02-17 19:59:24 +08:00
|
|
|
// Update AFEs
|
|
|
|
c.resources.afes.0.set_gain(settings.afe[0]);
|
|
|
|
c.resources.afes.1.set_gain(settings.afe[1]);
|
2021-06-09 21:25:59 +08:00
|
|
|
|
2021-06-29 19:23:42 +08:00
|
|
|
// Update the signal generators
|
2021-07-19 20:37:34 +08:00
|
|
|
for (i, &config) in settings.signal_generator.iter().enumerate() {
|
|
|
|
match config.try_into() {
|
|
|
|
Ok(config) => {
|
|
|
|
c.resources
|
|
|
|
.signal_generator
|
|
|
|
.lock(|generator| generator[i].update_waveform(config));
|
2021-07-19 19:01:31 +08:00
|
|
|
}
|
2021-07-19 20:37:34 +08:00
|
|
|
Err(err) => log::error!(
|
|
|
|
"Failed to update signal generation on DAC{}: {:?}",
|
|
|
|
i,
|
|
|
|
err
|
|
|
|
),
|
2021-07-19 19:01:31 +08:00
|
|
|
}
|
2021-07-19 20:37:34 +08:00
|
|
|
}
|
2021-06-28 19:16:54 +08:00
|
|
|
|
2021-06-09 21:25:59 +08:00
|
|
|
let target = settings.stream_target.into();
|
|
|
|
c.resources.network.direct_stream(target);
|
2021-01-26 21:28:06 +08:00
|
|
|
}
|
|
|
|
|
2021-05-05 20:42:17 +08:00
|
|
|
#[task(priority = 1, resources=[network, settings, telemetry], schedule=[telemetry])]
|
2021-04-15 20:40:47 +08:00
|
|
|
fn telemetry(mut c: telemetry::Context) {
|
2021-05-06 22:23:41 +08:00
|
|
|
let telemetry: TelemetryBuffer =
|
|
|
|
c.resources.telemetry.lock(|telemetry| *telemetry);
|
2021-04-15 20:40:47 +08:00
|
|
|
|
2021-05-07 19:04:25 +08:00
|
|
|
let (gains, telemetry_period) = c
|
|
|
|
.resources
|
|
|
|
.settings
|
|
|
|
.lock(|settings| (settings.afe, settings.telemetry_period));
|
2021-05-05 20:42:17 +08:00
|
|
|
|
2021-06-09 19:26:41 +08:00
|
|
|
c.resources
|
|
|
|
.network
|
|
|
|
.telemetry
|
2021-05-26 23:56:44 +08:00
|
|
|
.publish(&telemetry.finalize(gains[0], gains[1]));
|
2021-04-15 20:40:47 +08:00
|
|
|
|
|
|
|
// Schedule the telemetry task in the future.
|
2021-04-20 19:46:37 +08:00
|
|
|
c.schedule
|
|
|
|
.telemetry(
|
|
|
|
c.scheduled
|
|
|
|
+ SystemTimer::ticks_from_secs(telemetry_period as u32),
|
|
|
|
)
|
2021-04-15 20:40:47 +08:00
|
|
|
.unwrap();
|
|
|
|
}
|
|
|
|
|
2021-05-31 20:28:57 +08:00
|
|
|
#[task(priority = 1, resources=[network], schedule=[ethernet_link])]
|
|
|
|
fn ethernet_link(c: ethernet_link::Context) {
|
|
|
|
c.resources.network.processor.handle_link();
|
2021-06-09 19:26:41 +08:00
|
|
|
c.schedule
|
|
|
|
.ethernet_link(c.scheduled + SystemTimer::ticks_from_secs(1))
|
|
|
|
.unwrap();
|
2021-05-31 20:28:57 +08:00
|
|
|
}
|
|
|
|
|
2021-01-20 20:43:34 +08:00
|
|
|
#[task(binds = ETH, priority = 1)]
|
|
|
|
fn eth(_: eth::Context) {
|
2021-05-17 19:01:45 +08:00
|
|
|
unsafe { hal::ethernet::interrupt_handler() }
|
2021-01-20 20:43:34 +08:00
|
|
|
}
|
|
|
|
|
2021-05-26 23:56:44 +08:00
|
|
|
#[task(binds = SPI2, priority = 3)]
|
2021-01-20 20:43:34 +08:00
|
|
|
fn spi2(_: spi2::Context) {
|
2021-06-04 16:50:09 +08:00
|
|
|
panic!("ADC0 SPI error");
|
2021-01-20 20:43:34 +08:00
|
|
|
}
|
|
|
|
|
2021-05-26 23:56:44 +08:00
|
|
|
#[task(binds = SPI3, priority = 3)]
|
2021-01-20 20:43:34 +08:00
|
|
|
fn spi3(_: spi3::Context) {
|
2021-06-04 16:50:09 +08:00
|
|
|
panic!("ADC1 SPI error");
|
2021-01-20 20:43:34 +08:00
|
|
|
}
|
|
|
|
|
2021-05-26 23:56:44 +08:00
|
|
|
#[task(binds = SPI4, priority = 3)]
|
2021-01-20 20:43:34 +08:00
|
|
|
fn spi4(_: spi4::Context) {
|
2021-06-04 16:50:09 +08:00
|
|
|
panic!("DAC0 SPI error");
|
2021-01-20 20:43:34 +08:00
|
|
|
}
|
|
|
|
|
2021-05-26 23:56:44 +08:00
|
|
|
#[task(binds = SPI5, priority = 3)]
|
2021-01-20 20:43:34 +08:00
|
|
|
fn spi5(_: spi5::Context) {
|
2021-06-04 16:50:09 +08:00
|
|
|
panic!("DAC1 SPI error");
|
2021-01-20 20:43:34 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
extern "C" {
|
|
|
|
// hw interrupt handlers for RTIC to use for scheduling tasks
|
|
|
|
// one per priority
|
|
|
|
fn DCMI();
|
|
|
|
fn JPEG();
|
|
|
|
fn SDMMC();
|
|
|
|
}
|
|
|
|
};
|