2021-01-20 20:43:34 +08:00
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#![deny(warnings)]
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#![no_std]
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#![no_main]
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2021-01-27 02:14:23 +08:00
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use stm32h7xx_hal as hal;
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2021-01-20 20:43:34 +08:00
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2021-01-27 02:14:23 +08:00
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use stabilizer::hardware;
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2021-01-20 20:43:34 +08:00
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2021-03-03 22:01:28 +08:00
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use miniconf::{minimq, Miniconf, MqttInterface};
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2021-01-28 01:15:35 +08:00
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use serde::Deserialize;
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2021-01-20 20:43:34 +08:00
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use dsp::iir;
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2021-01-30 22:00:58 +08:00
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use hardware::{
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2021-02-17 23:53:53 +08:00
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Adc0Input, Adc1Input, AfeGain, CycleCounter, Dac0Output, Dac1Output,
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NetworkStack, AFE0, AFE1,
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2021-01-30 22:00:58 +08:00
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};
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2021-01-20 20:43:34 +08:00
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2021-02-02 00:18:10 +08:00
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const SCALE: f32 = i16::MAX as _;
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2021-01-20 20:43:34 +08:00
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// The number of cascaded IIR biquads per channel. Select 1 or 2!
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const IIR_CASCADE_LENGTH: usize = 1;
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2021-03-01 21:46:12 +08:00
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#[derive(Debug, Deserialize, Miniconf)]
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2021-01-28 01:15:35 +08:00
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pub struct Settings {
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2021-02-17 19:59:24 +08:00
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afe: [AfeGain; 2],
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iir_ch: [[iir::IIR; IIR_CASCADE_LENGTH]; 2],
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2021-01-28 01:15:35 +08:00
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}
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2021-02-17 19:59:24 +08:00
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impl Default for Settings {
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fn default() -> Self {
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Self {
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afe: [AfeGain::G1, AfeGain::G1],
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iir_ch: [[iir::IIR::new(1., -SCALE, SCALE); IIR_CASCADE_LENGTH]; 2],
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}
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2021-01-28 01:15:35 +08:00
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}
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2021-01-26 21:28:06 +08:00
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}
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2021-01-20 20:43:34 +08:00
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#[rtic::app(device = stm32h7xx_hal::stm32, peripherals = true, monotonic = rtic::cyccnt::CYCCNT)]
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const APP: () = {
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struct Resources {
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afes: (AFE0, AFE1),
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adcs: (Adc0Input, Adc1Input),
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dacs: (Dac0Output, Dac1Output),
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2021-02-17 19:08:03 +08:00
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mqtt_interface:
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MqttInterface<Settings, NetworkStack, minimq::consts::U256>,
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clock: CycleCounter,
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// Format: iir_state[ch][cascade-no][coeff]
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#[init([[[0.; 5]; IIR_CASCADE_LENGTH]; 2])]
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iir_state: [[iir::Vec5; IIR_CASCADE_LENGTH]; 2],
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#[init([[iir::IIR::new(1., -SCALE, SCALE); IIR_CASCADE_LENGTH]; 2])]
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iir_ch: [[iir::IIR; IIR_CASCADE_LENGTH]; 2],
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}
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#[init]
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fn init(c: init::Context) -> init::LateResources {
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// Configure the microcontroller
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let (mut stabilizer, _pounder) = hardware::setup(c.core, c.device);
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let mqtt_interface = {
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let mqtt_client = {
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2021-03-03 22:01:28 +08:00
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minimq::MqttClient::new(
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hardware::design_parameters::MQTT_BROKER.into(),
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"",
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stabilizer.net.stack,
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)
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.unwrap()
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};
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2021-03-03 02:04:39 +08:00
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MqttInterface::new(
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mqtt_client,
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"dt/sinara/stabilizer",
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Settings::default(),
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)
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.unwrap()
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};
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2021-01-31 01:57:06 +08:00
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2021-01-20 20:43:34 +08:00
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// Enable ADC/DAC events
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stabilizer.adcs.0.start();
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stabilizer.adcs.1.start();
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stabilizer.dacs.0.start();
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stabilizer.dacs.1.start();
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// Start sampling ADCs.
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stabilizer.adc_dac_timer.start();
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init::LateResources {
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mqtt_interface,
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afes: stabilizer.afes,
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adcs: stabilizer.adcs,
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dacs: stabilizer.dacs,
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clock: stabilizer.cycle_counter,
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}
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}
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/// Main DSP processing routine for Stabilizer.
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///
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/// # Note
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/// Processing time for the DSP application code is bounded by the following constraints:
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///
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/// DSP application code starts after the ADC has generated a batch of samples and must be
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/// completed by the time the next batch of ADC samples has been acquired (plus the FIFO buffer
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/// time). If this constraint is not met, firmware will panic due to an ADC input overrun.
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///
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/// The DSP application code must also fill out the next DAC output buffer in time such that the
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/// DAC can switch to it when it has completed the current buffer. If this constraint is not met
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/// it's possible that old DAC codes will be generated on the output and the output samples will
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/// be delayed by 1 batch.
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///
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/// Because the ADC and DAC operate at the same rate, these two constraints actually implement
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/// the same time bounds, meeting one also means the other is also met.
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#[task(binds=DMA1_STR4, resources=[adcs, dacs, iir_state, iir_ch], priority=2)]
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fn process(c: process::Context) {
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let adc_samples = [
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c.resources.adcs.0.acquire_buffer(),
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c.resources.adcs.1.acquire_buffer(),
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];
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let dac_samples = [
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c.resources.dacs.0.acquire_buffer(),
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c.resources.dacs.1.acquire_buffer(),
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];
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for channel in 0..adc_samples.len() {
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for sample in 0..adc_samples[0].len() {
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let x = f32::from(adc_samples[channel][sample] as i16);
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let mut y = x;
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for i in 0..c.resources.iir_state[channel].len() {
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y = c.resources.iir_ch[channel][i]
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.update(&mut c.resources.iir_state[channel][i], y);
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}
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// Note(unsafe): The filter limits ensure that the value is in range.
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// The truncation introduces 1/2 LSB distortion.
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let y = unsafe { y.to_int_unchecked::<i16>() };
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// Convert to DAC code
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dac_samples[channel][sample] = y as u16 ^ 0x8000;
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}
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}
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}
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2021-02-17 19:08:03 +08:00
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#[idle(resources=[mqtt_interface, clock], spawn=[settings_update])]
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fn idle(mut c: idle::Context) -> ! {
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let clock = c.resources.clock;
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loop {
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let sleep = c.resources.mqtt_interface.lock(|interface| {
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2021-03-15 18:41:13 +08:00
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match interface.network_stack().poll(clock.current_ms()) {
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Ok(updated) => !updated,
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Err(err) => {
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log::info!("Network error: {:?}", err);
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false
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}
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}
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});
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2021-03-05 00:26:10 +08:00
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match c
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.resources
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.mqtt_interface
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.lock(|interface| interface.update())
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{
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Ok(update) => {
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if update {
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c.spawn.settings_update().unwrap();
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} else if sleep {
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cortex_m::asm::wfi();
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}
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}
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Err(miniconf::MqttError::Network(
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smoltcp_nal::NetworkError::NoIpAddress,
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)) => {}
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Err(error) => log::info!("Unexpected error: {:?}", error),
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}
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}
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}
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2021-02-18 00:56:18 +08:00
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#[task(priority = 1, resources=[mqtt_interface, afes, iir_ch])]
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fn settings_update(mut c: settings_update::Context) {
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let settings = &c.resources.mqtt_interface.settings;
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// Update the IIR channels.
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c.resources.iir_ch.lock(|iir| *iir = settings.iir_ch);
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// Update AFEs
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c.resources.afes.0.set_gain(settings.afe[0]);
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c.resources.afes.1.set_gain(settings.afe[1]);
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2021-01-26 21:28:06 +08:00
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}
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2021-01-20 20:43:34 +08:00
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#[task(binds = ETH, priority = 1)]
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fn eth(_: eth::Context) {
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unsafe { hal::ethernet::interrupt_handler() }
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}
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#[task(binds = SPI2, priority = 3)]
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fn spi2(_: spi2::Context) {
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panic!("ADC0 input overrun");
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}
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#[task(binds = SPI3, priority = 3)]
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fn spi3(_: spi3::Context) {
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2021-03-02 02:49:21 +08:00
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panic!("ADC1 input overrun");
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}
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#[task(binds = SPI4, priority = 3)]
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fn spi4(_: spi4::Context) {
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panic!("DAC0 output error");
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}
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#[task(binds = SPI5, priority = 3)]
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fn spi5(_: spi5::Context) {
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panic!("DAC1 output error");
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}
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extern "C" {
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// hw interrupt handlers for RTIC to use for scheduling tasks
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// one per priority
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fn DCMI();
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fn JPEG();
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fn SDMMC();
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}
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};
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