Commit Graph

17 Commits

Author SHA1 Message Date
Donald Sebastian Leung 96d470921b Fix assertions for no replacements case 2020-10-21 14:03:35 +08:00
Donald Sebastian Leung b7a69557de Add assertion for no replacements given unique inputs 2020-10-21 13:09:54 +08:00
Donald Sebastian Leung 67130ed79e Add uniqueness assertion for case with no replacements 2020-10-21 12:40:16 +08:00
Donald Sebastian Leung d8c40ce382 Add failing trace and trace analysis 2020-10-20 13:05:38 +08:00
Donald Sebastian Leung 8fe67cf6f4 Skip assertions for configurable no. of clock cycles 2020-10-19 12:39:32 +08:00
Donald Sebastian Leung 5011245007 Increase BMC depth for sorting network assertions 2020-10-16 13:41:38 +08:00
Donald Sebastian Leung 036c91539b Start preparing assertions for sorting network 2020-10-16 12:18:09 +08:00
Donald Sebastian Leung 6746052a60 Add rtio.sed.output_driver 2020-10-09 11:16:01 +08:00
Donald Sebastian Leung 1d5945f7fa Add rtio.sed.output_network 2020-10-08 17:05:04 +08:00
Donald Sebastian Leung c2ee2fbdef Add rtio.sed.layouts 2020-10-08 11:06:35 +08:00
Donald Sebastian Leung 8d3c69ea08 Remove redundant files 2020-09-30 12:33:50 +08:00
Donald Sebastian Leung c9857bb831 Reset translation progress 2020-09-30 10:55:08 +08:00
Donald Sebastian Leung a3cdb44572 Add WIP implementation of rtio.sed.output_driver 2020-09-29 17:27:43 +08:00
Donald Sebastian Leung 36fb6306b0 Add rtio.sed.output_network 2020-09-29 16:35:59 +08:00
Donald Sebastian Leung 7c742dc2d1 Add rtio.sed.lane_distributor 2020-09-28 16:01:43 +08:00
Donald Sebastian Leung bf08fe1d50 Add partial implementation of lane distributor 2020-09-28 11:36:26 +08:00
Donald Sebastian Leung 1a83778590 Remove redundant 'artiq.gateware' from module names 2020-09-25 15:10:07 +08:00