artiq/artiq/gateware
Robert Jördens 170d2886fd Merge branch 'pdq'
* pdq:
  pdq: documentation
  pdq2 -> pdq
  pdq2: use 16 bit data, buffered read_mem()
  spi: style
  pdq2: mem_read
  pdq2: align subsequent writes to end
  sma_spi: undo cri_con
  pdq2: memory write, kernel_invariants
  sma_spi: cri/cd changes
  sma_spi: LVCMOS25
  coredevice.spi: kernel invariants and style
  sma_spi: free up user_sma pins
  sma_spi: add demo target with SPI on four SMA
  pdq2: memory write
  pdq2: crc/frame register accessors
  doc: pdq2 spi backend
  pdq2: config writes
2017-05-12 11:46:45 +02:00
..
amp firmware: don't build libdyld through misoc. 2017-03-14 08:33:31 +00:00
drtio drtio: collision/replace fixes 2017-04-06 16:33:49 +08:00
dsp fir: streamline, optimize DSP extraction, left-align inputs 2016-12-20 21:39:51 +01:00
rtio rtio: fix indentation 2017-04-06 12:08:13 +08:00
targets Merge branch 'pdq' 2017-05-12 11:46:45 +02:00
test drtio: test replace in RTL simulation 2017-04-06 16:33:59 +08:00
__init__.py artiqlib -> artiq.gateware 2015-03-08 11:00:24 +01:00
ad9_dds.py ad9xxx -> ad9_dds 2017-01-04 11:34:52 +01:00
ad9154_fmc_ebz.py Merge remote-tracking branch 'm-labs/phaser2' into phaser2 2016-12-02 14:11:56 +01:00
nist_clock.py gateware/nist_clock: increase DDS bus drive strength. Closes #468 2016-06-07 11:08:19 -04:00
nist_qc2.py qc2: swap SPI/TTL, all TTL lines are now In+Out compatible 2016-05-19 10:42:03 +08:00
spi.py spi: fix xfers with full data_width (closes #615) 2017-01-03 19:51:14 +01:00