Robert Jördens f4c6879c76 sawg: special case Config RTIO address		2017-06-22 10:26:29 +02:00
..
phy	sawg: special case Config RTIO address	2017-06-22 10:26:29 +02:00
__init__.py	rtio: export DMA and CRIInterconnectShared	2016-12-01 16:30:29 +08:00
analyzer.py	make collision and busy asynchronous errors, and simplify CPU/gateware handshake for output errors and reads	2017-03-27 16:32:23 +08:00
cdc.py	drtio: use BlindTransfer for error reporting	2017-04-03 00:18:07 +08:00
core.py	rtio: refactor RelaxedAsyncResetSynchronizer	2017-06-18 14:37:08 +02:00
cri.py	cri: add note about clearing of o_data	2017-06-16 19:06:00 +02:00
dma.py	gateware: simplify the CRI arbiter to use a plain mux.	2017-04-05 15:09:19 +00:00
moninj.py	moninj: do not require a rsys clock domain	2017-02-20 15:52:48 +08:00
rtlink.py	rtio: add support for latency compensation in phy	2016-12-14 19:16:07 +01:00