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154 Commits

Author SHA1 Message Date
Robert Jördens f4c6879c76 sawg: special case Config RTIO address 2017-06-22 10:26:29 +02:00
Robert Jördens 0d8067256b rtio: refactor RelaxedAsyncResetSynchronizer 2017-06-18 14:37:08 +02:00
Robert Jördens 424b2bfbd8 rtio: describe rio and rio_phy domains a bit more 2017-06-17 12:21:07 +02:00
Robert Jördens 219dfd8984 rtio: add one register level for rio and rio_phy resets 
* This should give Vivado some wiggle room during PnR.
* It needs three new clock domains which is ugly. But since
AsyncResetSynchronizer can only drive clock domains resets directly
there seems to be no other way to add one register level currently.
 2017-06-17 12:17:48 +02:00
Robert Jördens 2a76034fbc cri: add note about clearing of o_data 2017-06-16 19:06:00 +02:00
Sebastien Bourdeauducq 9ab63920e0 Remove Pipistrello support 
Closes #658
Closes #381
 2017-05-15 17:17:44 +08:00
Sebastien Bourdeauducq c0100ebc56 rtio: fix indentation 2017-04-06 12:08:13 +08:00
Sebastien Bourdeauducq 207453efcd rtio: add a missing case for collision reporting 2017-04-06 11:28:16 +08:00
whitequark 47632f81b1 gateware: CRIArbiter -> CRISwitch. 2017-04-05 16:10:39 +00:00
whitequark 391660e545 gateware: simplify the CRI arbiter to use a plain mux. 2017-04-05 15:09:19 +00:00
Sebastien Bourdeauducq 12249dac57 rtio: do not clear asynchronous error flags on RTIO reset 2017-04-03 00:20:30 +08:00
Sebastien Bourdeauducq db3118b916 drtio: use BlindTransfer for error reporting 2017-04-03 00:18:07 +08:00
Sebastien Bourdeauducq b74d6fb9ba make collision and busy asynchronous errors, and simplify CPU/gateware handshake for output errors and reads 2017-03-27 16:32:23 +08:00
whitequark 4de336fbe9 gateware: reverse bytes of SDRAM word, not bits. 2017-03-17 11:16:46 +00:00
whitequark 6b63322106 gateware: reverse SDRAM words in RTIO DMA engine. 2017-03-17 07:29:28 +00:00
whitequark 4b14887ddb gateware: work around ISE/Vivado bugs with very wide shifts. 2017-03-17 07:29:28 +00:00
Sebastien Bourdeauducq a7de58b604 rtio: Inout → InOut 2017-03-14 14:18:55 +08:00
Sebastien Bourdeauducq 497c795d8c drtio: input support (untested) 2017-03-13 23:54:44 +08:00
Sebastien Bourdeauducq 1e6a33b586 rtio: handle input timeout in gateware 
The information passed by the runtime will be used by the DRTIO core
to poll the remote side appropriately.
 2017-03-03 17:37:47 +08:00
Sebastien Bourdeauducq d2f2415b50 analyzer: use CRI and connect at RTIO core 
This causes DMA events to be included in analyzer traces.
 2017-03-02 18:47:56 +08:00
Sebastien Bourdeauducq 7d6ebabc1b reorganize core device communication code 2017-02-27 18:37:30 +08:00
Sebastien Bourdeauducq c66efc0279 moninj: do not require a rsys clock domain 2017-02-20 15:52:48 +08:00
Sebastien Bourdeauducq 86f6b391b7 ad9xxx -> ad9_dds 2017-01-04 11:34:52 +01:00
Sebastien Bourdeauducq 6b998581cc rtio: use same reset for counter_rtio whatever the interface delay is 2016-12-15 09:28:13 +08:00
Robert Jördens 8381db279f sawg: wire up all HBF outputs, latency compensation in phys, simplify 2016-12-14 19:16:07 +01:00
Robert Jördens 6cdb96c5e0 rtio: add support for latency compensation in phy 
* if multiple RTIO channels influence the same data stream and physical
output channel (see SAWG) differential latency needs to be compensated
* this is a NOP for phys with zero delay (default)
* if delay==1, it adds one timestamp-wide register
* if delay >1, it adds one adder and one register
* latency compensation using (~10-50 deep) delay lines is about as
expensive as a single adder+register but very tedious to implement
 2016-12-14 19:16:07 +01:00
Robert Jördens c63fa46430 Merge branch 'phaser2' 
* phaser2: (157 commits)
  sawg/hbf: tweak pipeline for timing
  fir: register multiplier output
  conda/phaser: build-depend on numpy
  sawg: reduce coefficient width
  sawg: fix latency
  test/fir: needs mpl. don't run by default
  test/sawg: patch spline
  sawg: use ParallelHBFCascade to AA [WIP]
  fir: add ParallelHBFCascade
  fir: add ParallelFIR and test
  gateware/dsp: add FIR and test
  README_PHASER: update
  sawg: documentation
  sawg: extract spline
  sawg: document
  sawg: demo_2tone
  sawg: round to int64
  gateware/phaser -> gateware/ad9154_fmc_ebz
  phaser: fix typo
  sawg: merge set/set64
  ...
 2016-12-12 17:31:39 +01:00
Sebastien Bourdeauducq 7196bc21c1 rtio: simplify error reset logic 
Channel is always selected when reset is issued.
 2016-12-12 17:35:10 +08:00
Sebastien Bourdeauducq bc36bda94a perform RTIO init on comms CPU side 2016-12-09 14:16:55 +08:00
Sebastien Bourdeauducq f3c50a37ca rtio: always read full DMA sequence 2016-12-06 01:05:47 +08:00
Sebastien Bourdeauducq c413d95b49 rtio: fix DMA get_csrs 2016-12-05 18:12:09 +08:00
Sebastien Bourdeauducq b677c69faf rtio: fix handling of o_status in DMA 2016-12-05 18:01:48 +08:00
Sebastien Bourdeauducq 75ea13748a rtio: fix DMA data MSB and stop signaling, self-checking unittest 2016-12-05 18:01:48 +08:00
Sebastien Bourdeauducq a5834765d0 rtio: more DMA fixes, better stopping mechanism 2016-12-05 18:01:48 +08:00
Sebastien Bourdeauducq 30bce5ad35 rtio: DMA fixes 2016-12-05 18:01:48 +08:00
Sebastien Bourdeauducq 88ad054ab6 Merge branch 'drtio' 2016-12-03 23:25:17 +08:00
Sebastien Bourdeauducq 3931d8097b rtio: fix DMA TimeOffset stream.connect 2016-12-01 16:43:46 +08:00
Sebastien Bourdeauducq 7c59688a12 rtio: simple DMA fixes 2016-12-01 16:30:48 +08:00
Sebastien Bourdeauducq 46dbc44c8f rtio: export DMA and CRIInterconnectShared 2016-12-01 16:30:29 +08:00
Sebastien Bourdeauducq 6c97a97d8c rtio: support single-master CRI arbiter 2016-12-01 16:30:11 +08:00
Sebastien Bourdeauducq a318243083 rtio: CRI arbiter (untested) 2016-12-01 15:41:43 +08:00
Sebastien Bourdeauducq cd3f68ba76 rtio: DMA core (untested) 2016-11-30 18:43:19 +08:00
Sebastien Bourdeauducq 85f2467e2c rtio: fix RTIO/DRTIO timestamp resolution discrepancy 2016-11-28 15:01:46 +08:00
Sebastien Bourdeauducq 5460202220 drtio: typo 2016-11-28 14:35:21 +08:00
Sebastien Bourdeauducq 4e1b497742 drtio: typo 2016-11-28 14:34:58 +08:00
Sebastien Bourdeauducq c419c422fa drtio: support for local RTIO core 2016-11-28 14:33:26 +08:00
Robert Jördens 1c84d1ee59 Merge branch 'master' into phaser2 
* master:
  rtio: support differential ttl
  RELEASE_NOTES: int(a, width=b) removal, use int32/64
  pc_rpc: use ProactorEventLoop on Windows (#627)
 2016-11-24 15:05:49 +01:00
Robert Jördens 95c885b580 rtio: support differential ttl 2016-11-24 15:04:12 +01:00
Sebastien Bourdeauducq 2d62a89143 rtio: use large data register 2016-11-23 23:23:27 +08:00
Sebastien Bourdeauducq 9941f3557d rtio: use only CRI commands for rio/rio_phy resets 2016-11-23 23:19:14 +08:00