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artiq
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268 Commits

Author SHA1 Message Date
Robert Jördens 67715f0d2e pipistrello: only put serdes on the lower ttls 
this setup is getting a bit power hungry.

pmt0, 1 (rtio channels 0, 1): 4x in and out
ttl0, 1 (rtio channels 2, 3): 4x out
ttl2 (rtio channel 4): 8x out
 2015-07-28 12:54:31 -06:00
Robert Jördens 9dfbf07743 pipistrello: use 4x serdes for rtio ttl 
pipistrello: do not wait for lock on startup

LCK_cycle:6 was added in 6a412f796e1 (mibuild). It waits for _all_
DCM and PLLs to lock (probably irrespective of STARTUP_WAIT).
 2015-07-28 12:54:27 -06:00
Sebastien Bourdeauducq 8e391e2661 kc705: generate 10MHz clock on GPIO SMA 
For SynthNV and input tests.
 2015-07-28 18:56:47 +08:00
Robert Jördens 1809a70f5c Revert "pipistrello: use 4x serdes for rtio ttl" 
This reverts commit 8e92cc91f5.

Broken. Will revisit.
 2015-07-27 23:39:35 -06:00
Robert Jördens f0a7078336 Revert "rtiocrg.c: pipistrello also has pll_reset" 
This reverts commit bdee914828.
 2015-07-27 22:18:45 -06:00
Robert Jördens bdee914828 rtiocrg.c: pipistrello also has pll_reset 2015-07-27 22:14:42 -06:00
Robert Jördens e95b06e96d pipistrello: tie unused dds.p low 2015-07-27 21:48:56 -06:00
Robert Jördens 8e92cc91f5 pipistrello: use 4x serdes for rtio ttl 2015-07-27 21:29:50 -06:00
Sebastien Bourdeauducq ae3a52c49c runtime: fix KERNELCPU_PAYLOAD_ADDRESS 2015-07-28 02:12:14 +08:00
whitequark eec4a2d2d2 Update buildsystem to track -fPIC and ranlib removal in MiSoC. 2015-07-27 21:10:46 +03:00
Sebastien Bourdeauducq 0cd74533ca runtime: more explicit message about startup clock failure 2015-07-28 00:38:38 +08:00
Sebastien Bourdeauducq 7feaca7c7c runtime: allow selecting external clock at startup 2015-07-28 00:19:07 +08:00
Sebastien Bourdeauducq 09d837e4ba runtime: monitor RTIO clock status 2015-07-28 00:05:24 +08:00
Sebastien Bourdeauducq 299bc1cb7e kc705: output divided-by-2 RTIO clock 2015-07-27 20:46:44 +08:00
Sebastien Bourdeauducq 256e99f0d7 kc705: crg cleanup 2015-07-27 20:31:37 +08:00
Sebastien Bourdeauducq 2a95e866aa kc705: use 8X SERDES RTIO PHY 2015-07-27 20:12:17 +08:00
Sebastien Bourdeauducq fe57308e71 runtime: support for RTIO PLL 2015-07-27 20:11:31 +08:00
Sebastien Bourdeauducq 117b361a06 Merge branch 'master' of github.com:m-labs/artiq 2015-07-27 11:42:29 +08:00
Sebastien Bourdeauducq 3573fd02a6 targets/kc705: add TIG constraints for ISE 2015-07-27 10:58:19 +08:00
Sebastien Bourdeauducq fe6a5c42df rtio: remove unused clk_freq argument 2015-07-27 10:57:15 +08:00
Sebastien Bourdeauducq d3f05e414a runtime: account for RTIO_FINE_TS_WIDTH in time buffers 2015-07-27 10:50:25 +08:00
Robert Jördens d65d303ac6 pipistrello: remove unused constraint kwarg 2015-07-26 17:39:07 -06:00
whitequark 1d9f40833d Update ldscripts with -fPIC support. 2015-07-26 16:16:48 +03:00
Sebastien Bourdeauducq aba2d3f112 runtime: process essential kernel CPU messages at all time 2015-07-25 16:26:04 +08:00
Sebastien Bourdeauducq 34aacd3c5f complete AD9914 support (no programmable modulus, untested) 2015-07-08 17:22:43 +02:00
Sebastien Bourdeauducq 8a33d8c868 never stop RTIO counter 2015-07-07 15:29:38 +02:00
Sebastien Bourdeauducq d20fb5abb2 remove workaround 2015-07-07 13:46:14 +02:00
Robert Jördens 959ba99f1c pipistrello: try simpler constraints 2015-07-04 21:08:28 -06:00
Sebastien Bourdeauducq 753d61b38f complete support for TTL clock generator 2015-07-04 18:36:01 +02:00
Sebastien Bourdeauducq 0a9f9093f7 kc705: fix ttl15 2015-07-02 20:02:05 +02:00
Sebastien Bourdeauducq 2881d5f00a gateware: add RTIO clock generator 2015-07-02 18:20:26 +02:00
Robert Jördens 3ee2bd5fa8 pipistrello: set CLKFX_MD_MAX from MD ratio 2015-06-29 12:59:59 -06:00
Robert Jördens d1c4cf0b78 pipistrello: update rtio channel doc 2015-06-29 12:21:54 -06:00
Robert Jördens f0ac8cb354 pipistrello: add user_led:2 for debugging w/o adapter 2015-06-29 11:30:37 -06:00
Robert Jördens d39382eca0 pipistrello: ext_led fifo depth 4 2015-06-28 22:06:33 -06:00
Robert Jördens 165ef20ffa pipistrello: drop rtio fifos for invisible leds 
the main board leds are all under the adapter board

also tweak fifo depths a bit in a feeble attempt to circumvent a ISE hang (par
phase 4)
 2015-06-28 21:24:57 -06:00
Robert Jördens e2cb0e107f pipistrello: really do not request xtrig 2015-06-28 21:11:41 -06:00
Robert Jördens 23eee94458 pipistrello: add notes to nist_qc1 about dds_clock 
* remove xtrig from the target as it is not usually connected (used for
  dds_clock) and ignore PMT2/BTN2 as C:15 is used for dds_clock.
* this also aligns the ttl channel numbers with kc705/nist_qc1 (two pmt
  inputs followed by 16 ttl outputs followed by leds)
 2015-06-28 20:56:12 -06:00
Sebastien Bourdeauducq 944bfafefa soc: support QC2 and AD9914 (untested) 2015-06-28 21:37:27 +02:00
Sebastien Bourdeauducq b6310b72db runtime: fix log formatting 2015-06-28 17:29:52 +02:00
Sebastien Bourdeauducq 8b5b219a18 runtime: provide fixdfdi 2015-06-27 23:51:48 +02:00
Sebastien Bourdeauducq 3bd7f11737 update lwip 2015-06-27 22:48:41 +02:00
Sebastien Bourdeauducq 2d475e146b runtime/flash_storage: use log not printf 2015-06-27 22:47:36 +02:00
Sebastien Bourdeauducq a7bbcdc1ad targets/pipistrello: mon -> moninj 2015-06-27 21:15:17 +02:00
Robert Jördens 5b3eac1d96 pipistrello: tweak fifo depths a bit 
ise being dull again, inferring all but one 64x64 fifo as bram...
minimum bram depth is 256 anyway
 2015-06-22 23:25:07 -06:00
Robert Jördens cd249b2f66 pipistrello: run at 83+1/3 MHz, cleanup CRG 2015-06-22 19:03:00 -06:00
Sebastien Bourdeauducq 9f3f9255a2 soc: increase DDS output FIFO sizes 2015-06-21 08:40:10 -06:00
Sebastien Bourdeauducq 87ea1433d3 dds: all working 2015-06-20 18:42:39 -06:00
Sebastien Bourdeauducq 5a9bdb2e33 DDS monitoring 2015-06-19 15:30:17 -06:00
Sebastien Bourdeauducq 03fe71228b dds: phase computation fixes 2015-06-19 11:01:43 -06:00