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artiq
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pipistrello: tweak fifo depths a bit 

ise being dull again, inferring all but one 64x64 fifo as bram...
minimum bram depth is 256 anyway
This commit is contained in:
Robert Jördens 2015-06-22 23:24:30 -06:00
parent cd249b2f66
commit 5b3eac1d96
1 changed files with 4 additions and 4 deletions
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8
soc/targets/artiq_pipistrello.py
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@ -99,21 +99,21 @@ trce -v 12 -fastpaths -tsi {build_name}.tsi -o {build_name}.twr {build_name}.ncd
phy = ttl_simple.Inout(platform.request("xtrig", 0))
self.submodules += phy
rtio_channels.append(rtio.Channel.from_phy(phy))
rtio_channels.append(rtio.Channel.from_phy(phy, ififo_depth=4))
for i in range(16):
phy = ttl_simple.Output(platform.request("ttl", i))
self.submodules += phy
rtio_channels.append(rtio.Channel.from_phy(phy))
rtio_channels.append(rtio.Channel.from_phy(phy, ofifo_depth=256))
phy = ttl_simple.Output(platform.request("ext_led", 0))
self.submodules += phy
rtio_channels.append(rtio.Channel.from_phy(phy))
rtio_channels.append(rtio.Channel.from_phy(phy, ofifo_depth=4))
for i in range(2, 5):
phy = ttl_simple.Output(platform.request("user_led", i))
self.submodules += phy
rtio_channels.append(rtio.Channel.from_phy(phy))
rtio_channels.append(rtio.Channel.from_phy(phy, ofifo_depth=4))
self.add_constant("RTIO_TTL_COUNT", len(rtio_channels))
self.add_constant("RTIO_DDS_CHANNEL", len(rtio_channels))