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artiq
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pipistrello: really do not request xtrig

This commit is contained in:
Robert Jördens 2015-06-28 21:11:41 -06:00
parent 23eee94458
commit e2cb0e107f
1 changed files with 0 additions and 5 deletions
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5
soc/targets/artiq_pipistrello.py
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@ -98,11 +98,6 @@ trce -v 12 -fastpaths -tsi {build_name}.tsi -o {build_name}.twr {build_name}.ncd
rtio_channels.append(rtio.Channel.from_phy(phy, ififo_depth=512,
ofifo_depth=4))
phy = ttl_simple.Inout(platform.request("xtrig"))
self.submodules += phy
rtio_channels.append(rtio.Channel.from_phy(phy, ififo_depth=4,
ofifo_depth=4))
for i in range(16):
phy = ttl_simple.Output(platform.request("ttl", i))
self.submodules += phy