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eed64a6d6b
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conda: fix openocd dependency
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2018-02-21 10:35:31 +08:00 |
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f060d6e1b3
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drtio: increase A7 clock aligner check period
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2018-02-20 18:50:35 +08:00 |
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738654c783
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drtio: support remote RTIO resets
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2018-02-20 18:48:54 +08:00 |
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f15b4bdde7
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style
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2018-02-20 18:47:59 +08:00 |
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7d9c7ada71
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drtio: fix test infinite loop
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2018-02-20 17:42:00 +08:00 |
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ad2c9590d0
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drtio: rewrite/fix reset and link bringup/teardown
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2018-02-20 17:26:43 +08:00 |
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bfabf3c906
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conda: bump migen (9c3a301)
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2018-02-19 13:07:17 +00:00 |
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7e02d8245c
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kasli: false paths
* don't bother with the round trip OSERDESE2 -> ... -> pad -> ... ->
ISERDESE2
* clock groups with derived clocks c.f. migen 9c3a301
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2018-02-19 13:05:11 +00:00 |
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0f4549655b
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sayma: use Xilinx RX synchronizer
Cannot be used on Kasli, this breaks the bitstream entirely (nothing on UART).
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2018-02-19 17:49:53 +08:00 |
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52049cf36a
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drtio: add Xilinx RX synchronizer
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2018-02-19 17:49:43 +08:00 |
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3bc575bee7
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drtio: add missing define for Sayma master
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2018-02-19 17:11:21 +08:00 |
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7376ab0ff8
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drtio: fix Sayma after 83abdd28
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2018-02-19 17:10:55 +08:00 |
|
Florent Kermarrec
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f5831af535
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drtio/transceiver/gtp_7series_init: don't reset gtp rx on power down
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2018-02-19 10:03:19 +01:00 |
|
Florent Kermarrec
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89a158c0c9
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drtio/transceiver/gtp_7series_init: remove dead code
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2018-02-19 10:02:23 +01:00 |
|
Florent Kermarrec
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782051f474
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drtio/transceiver/gtp_7series_init: add no retiming on gtp resets
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2018-02-19 09:59:50 +01:00 |
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01fa6c1c2e
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reorganize examples
|
2018-02-19 15:46:08 +08:00 |
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4b4090518b
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drtio: clean up remnants of removed debug functions
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2018-02-19 15:14:32 +08:00 |
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c329c83676
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kasli: fix disable_si5324_ibuf no_retiming
|
2018-02-19 12:19:05 +08:00 |
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a93decdef2
|
kasli: disable DRTIO IBUFDS_GTE2 until Si5324 is initialized
|
2018-02-19 00:48:37 +08:00 |
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94c20dfd4d
|
drtio: fix misleading GenericRXSynchronizer comment
|
2018-02-19 00:47:54 +08:00 |
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83abdd283a
|
drtio: signal stable clock input to transceiver
|
2018-02-18 22:29:30 +08:00 |
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c87636ed2b
|
si5324: fix cfb21ca
|
2018-02-18 11:38:20 +01:00 |
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caedcd5a15
|
ad9912: cleanup, document init()
|
2018-02-18 11:38:16 +01:00 |
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75c89422c9
|
ad991[02]: sysclk can be 1 GHz
|
2018-02-18 10:29:19 +00:00 |
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6ae1cc20aa
|
conda: bump misoc (#908)
|
2018-02-18 12:35:49 +08:00 |
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41adbef9a9
|
conda: bump misoc
|
2018-02-17 17:41:16 +08:00 |
|
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287d533437
|
Revert "sayma_amc: remove RTM bitstream upload core. Closes #908"
This reverts commit 2d4a1340ea.
|
2018-02-17 17:38:48 +08:00 |
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73985a9215
|
sayma: remove constraints at outputs of serwb PLL (see misoc d1489ed)
|
2018-02-17 17:38:17 +08:00 |
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|
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039dee4c8e
|
si5324: rename SI5324_FREE_RUNNING to SI5324_AS_SYNTHESIZER
The previous name was causing confusion with the FREE_RUN bit
that connects the crystal to CLKIN2.
|
2018-02-17 13:54:50 +08:00 |
|
|
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cfb21ca126
|
si5324: fix usage of external CLKIN2 reference
|
2018-02-17 13:52:01 +08:00 |
|
|
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07a31f8d86
|
conda: bump openocd
|
2018-02-17 13:21:10 +08:00 |
|
|
|
fb8b36cd41
|
clean up ccc279b8
|
2018-02-17 12:10:46 +08:00 |
|
hartytp
|
ccc279b8da
|
rewrite HMC7043 init code without using ADI GUI outputs, working analog/digital delay
|
2018-02-17 12:07:11 +08:00 |
|
|
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e41f49cc75
|
kasli: opticlock 125 MHz, mark external reference case broken
|
2018-02-16 17:23:15 +00:00 |
|
|
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e4db84e214
|
doc: fix typo
|
2018-02-17 00:11:48 +08:00 |
|
|
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7a5161d348
|
conda: bump misoc (#902)
|
2018-02-17 00:11:42 +08:00 |
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|
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0ef33dd0d8
|
manual: add note about the "correct" vivado version
close #910
|
2018-02-15 14:21:17 +01:00 |
|
|
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7002bea0ab
|
kasli: clean up urukul example more
|
2018-02-15 14:21:17 +01:00 |
|
|
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4d42df2a7c
|
kasli: set up Si5324 in standalone operation
|
2018-02-15 20:32:58 +08:00 |
|
|
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c5ae81f452
|
satman: remove unused 62.5MHz Si5324 settings
|
2018-02-15 20:29:51 +08:00 |
|
|
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d7387611c0
|
sayma: print RTM gateware version
|
2018-02-15 19:31:58 +08:00 |
|
whitequark
|
d572c0c34d
|
artiq_devtool: fix the hotswap action.
|
2018-02-14 23:10:27 +00:00 |
|
whitequark
|
fe50018037
|
firmware: make network tracing runtime switchable.
|
2018-02-14 23:03:20 +00:00 |
|
|
|
2adba3ed33
|
urukul: document ad9912, and cpld, fix api
|
2018-02-14 09:45:17 +01:00 |
|
|
|
ede98679fc
|
ad9910: add documentation
|
2018-02-14 09:05:03 +01:00 |
|
|
|
b6395a809b
|
kasli: remove old urukul test code
|
2018-02-13 22:16:57 +01:00 |
|
|
|
be693bc8a9
|
opticlock: examples
|
2018-02-13 22:13:40 +01:00 |
|
|
|
a3d136d30d
|
opticlock: wire urukul and novogorny
|
2018-02-13 22:13:40 +01:00 |
|
|
|
7f1bfddeda
|
ad9910: tweak spi timing for higher speed
|
2018-02-13 22:13:40 +01:00 |
|
|
|
6a6695924f
|
urukul: proto 8
|
2018-02-13 22:13:40 +01:00 |
|
