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fb8c779b4f
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artiq_flash: report XADC data
* bump openocd
* only kasli, kc705, sayma rtm so far
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2018-01-30 14:56:50 +08:00 |
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whitequark
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807eb1155b
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Update smoltcp.
Fixes #902.
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2018-01-30 03:29:08 +00:00 |
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whitequark
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a669652854
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artiq_flash: tell openocd to not listen on any network ports.
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2018-01-30 03:12:06 +00:00 |
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whitequark
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0edc34a9e5
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artiq_devtool: the proxy artiq_flash action doesn't exist anymore.
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2018-01-28 15:19:17 +00:00 |
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whitequark
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9a94482c6e
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conda: fix typo in 885ab409.
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2018-01-28 15:18:52 +00:00 |
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whitequark
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79ea454ec1
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conda: use $SP_DIR instead of $PREFIX/lib/python3.5/site-packages. (#652)
This removes the last hardcoded python3.5 reference.
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2018-01-28 14:29:19 +00:00 |
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whitequark
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885ab40946
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conda: split RTM and AMC packages back.
This avoids multiplying the RTM compilation time by the number
of AMC packages.
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2018-01-28 14:27:55 +00:00 |
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whitequark
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11a8b84355
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Merge the build trees of sayma_amc and sayma_rtm targets.
This also makes them a single artiq_flash target, and a single
conda package.
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2018-01-27 19:54:31 +00:00 |
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whitequark
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0b9c551962
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artiq_flash: implement flash read functionality.
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2018-01-27 19:54:31 +00:00 |
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0aacdb0458
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tools: add missing import
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2018-01-28 02:12:46 +08:00 |
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6f90a43df2
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examples: reorganize for new hardware
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2018-01-28 02:11:45 +08:00 |
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67625fe912
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test: check kernel overhead credibility
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2018-01-28 01:02:03 +08:00 |
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e8ed3475ea
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test: add kernel overhead test (#407)
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2018-01-28 01:00:59 +08:00 |
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3231d8b235
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RELEASE_NOTES: 3.3
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2018-01-28 00:18:01 +08:00 |
|
whitequark
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eed2db3a98
|
artiq_flash: make the proxy action unnecessary.
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2018-01-27 15:43:27 +00:00 |
|
whitequark
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d58393a1e5
|
runtime: build with -Cpanic=unwind.
This is required for backtraces to function. I'm not sure how it
turned out that master had -Cpanic=abort.
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2018-01-26 23:01:24 +00:00 |
|
whitequark
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08101b631d
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artiq_devtool: fix typo.
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2018-01-26 13:55:31 +00:00 |
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440e19b8f9
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kasli: use SFP2 for DRTIO mastering
SFP1 PCB routing has some issues.
Also use SFP1 LED for DRTIO in both master and satellite.
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2018-01-26 19:02:54 +08:00 |
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c9b36e3559
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conda: bump misoc, close #905
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2018-01-25 19:31:26 +01:00 |
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0d2f89db53
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si5324: chip does not ack RST_REG write
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2018-01-25 11:06:19 +08:00 |
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ca4d5ae73e
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artiq_flash: add kasli drtio variants
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2018-01-25 00:00:07 +08:00 |
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77f90cf93b
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test: relax RTIO counter test and print result
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2018-01-24 10:07:22 +08:00 |
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ed0fbd5662
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test: add test for RTIO counter (#883)
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2018-01-24 00:28:39 +08:00 |
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e0e795f11c
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sayma_amc: constrain pin, remove keep
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2018-01-23 15:42:47 +00:00 |
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ee14912042
|
conda: bump migen/misoc (vivado constraints)
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2018-01-23 16:23:12 +01:00 |
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b5c035bb52
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sayma_rtm: constrain serwb clock input
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2018-01-23 13:54:53 +00:00 |
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aada38f508
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kasli, kc705: remove vivado "keep", cleanup a constraint
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2018-01-23 13:15:26 +00:00 |
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85102e191e
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sayma_rtm: derive clocks automatically
* also don't add false paths unless necessary
|
2018-01-23 11:00:55 +00:00 |
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7d1b3f37c9
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sayma_rtm: set CFGBVS/CONFIG_VOLTAGE, compress
|
2018-01-23 10:56:42 +00:00 |
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cb0016ceee
|
examples/sayma: fix ref_multiplier
SAWG is working, whoohoo!
|
2018-01-23 15:26:03 +08:00 |
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cfffd9e13d
|
si5324: kasli support
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2018-01-23 13:17:03 +08:00 |
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649deccd9b
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kasli: fix DRTIO satellite QPLL refclksel
|
2018-01-23 12:27:19 +08:00 |
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4b4374f76a
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sayma: register_jref for JESD204. Closes #904
|
2018-01-23 12:19:15 +08:00 |
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763aefacff
|
kasli: fix typo
|
2018-01-23 12:10:54 +08:00 |
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c7b148a704
|
kasli: when using both GTP clocks, send REFCLK0 to PLL0 and REFCLK1 to PLL1
|
2018-01-23 12:08:10 +08:00 |
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d6157514c7
|
gtp_7series: flexible QPLL channel selection
|
2018-01-23 12:03:09 +08:00 |
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9f87c34a94
|
kasli: fix QPLL instantiation
|
2018-01-23 10:39:31 +08:00 |
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98a5607634
|
gtp_7series: set clock muxes correctly for second QPLL channel
|
2018-01-23 10:39:20 +08:00 |
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25fee1a0bb
|
gtp_7series: use QPLL second channel
|
2018-01-23 10:15:49 +08:00 |
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031d7ff020
|
kasli: keep using second QPLL channel for DRTIO satellite
|
2018-01-23 10:13:10 +08:00 |
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626075cbc1
|
gtp_7series: simplify TX clocking
|
2018-01-23 09:49:23 +08:00 |
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472840f16b
|
conda: bump migen/misoc
* kasli clock constraint
* vivado false paths
|
2018-01-22 20:32:18 +01:00 |
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74b7baa8c5
|
urukul example: mmcx clock input
|
2018-01-22 20:30:08 +01:00 |
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a86b28def2
|
urukul: example additions
* relax timings for faster spi xfers
* continuous readback test to explore spi speed limit
|
2018-01-22 20:29:30 +01:00 |
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5a9035b122
|
urukul: faster spi clock
|
2018-01-22 18:27:40 +00:00 |
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ca1fdaa190
|
ad9910: relax timing for faster spi clock
|
2018-01-22 18:27:40 +00:00 |
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0d73401365
|
conda: bump migen+misoc
|
2018-01-23 01:28:10 +08:00 |
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401e57d41c
|
gtp_7series: fix nchannels assert
|
2018-01-23 01:28:01 +08:00 |
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aa62e91487
|
kasli: add DRTIO targets (no firmware)
|
2018-01-23 01:27:40 +08:00 |
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296ac35f5d
|
sayma_amc: SFP TX disable is active-high
|
2018-01-23 00:32:09 +08:00 |
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