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6403 Commits

Author SHA1 Message Date
Sebastien Bourdeauducq 28fb0fd754 sayma: add SYSREF sampler gateware 2018-06-20 17:48:35 +08:00
Sebastien Bourdeauducq 814d0583db hmc7043: improve smoothness of sysref phase control 2018-06-20 17:40:48 +08:00
Sebastien Bourdeauducq 9142a5ab8a rtio: expose coarse timestamp in RTIO and DRTIO satellite cores 2018-06-20 17:39:54 +08:00
Sebastien Bourdeauducq 5272c11704 typo 2018-06-20 17:05:20 +08:00
Sebastien Bourdeauducq 0c32d07e8b ad9154: new sysref scan 
Print margins around the pre-defined fixed phase.
Also report error if margins are too small.

The fixed phase is also changed by this commit (the value 88 is
from before the new HMC7043 initialization code, and is probably wrong).
 2018-06-20 00:15:58 +08:00
Sebastien Bourdeauducq 4803ca3799 examples/sayma_drtio: add SAWG channels 2018-06-19 23:50:26 +08:00
Sebastien Bourdeauducq 3d0e92aefd hmc7043: check that chip is disabled at startup 2018-06-19 23:49:17 +08:00
Sebastien Bourdeauducq 740e6863c3 hmc7043: add delay after releasing hardware reset 2018-06-19 23:48:48 +08:00
Sebastien Bourdeauducq 75b6cea52f sayma: add SAWG to DRTIO satellite 2018-06-19 19:12:10 +08:00
Sebastien Bourdeauducq eb3259b847 firmware: reduce number of DAC initialization attempts 
Faster startup when one DAC is broken.
 2018-06-19 19:10:23 +08:00
Sebastien Bourdeauducq 1d594d0c97 firmware: make DAC initialization failures non-fatal 
This allows using RTMs with one broken DAC for development.
 2018-06-19 19:09:38 +08:00
Sebastien Bourdeauducq 158b5e3083 satman: program Allaki 2018-06-19 18:09:05 +08:00
Sebastien Bourdeauducq 574892a4e5 firmware/serwb: cleanup and improve messaging 2018-06-19 15:11:03 +08:00
Sebastien Bourdeauducq c862471165 typo 2018-06-19 14:35:24 +08:00
Sebastien Bourdeauducq 433273dd95 sayma: support RTM FPGA, HMC830 and HMC7043 in DRTIO master and satellite 2018-06-19 14:33:48 +08:00
Sebastien Bourdeauducq 476cfa0f53 si5324: improve lock messaging 2018-06-19 14:29:57 +08:00
Sebastien Bourdeauducq 6403a0d5d1 sayma_amc: update without-sawg description 2018-06-19 13:52:05 +08:00
Sebastien Bourdeauducq d29b3dd588 hmc830: compile-time configurable reference frequency 2018-06-19 13:47:32 +08:00
Sebastien Bourdeauducq 6f3ed81626 targets/sayma_rtm: fix description 2018-06-18 17:46:53 +08:00
Robert Jördens 21a48711ec i2c: refactor common operations 2018-06-18 09:34:09 +00:00
Sebastien Bourdeauducq 0e640a6d6f hmc7043: fix SYSREF to meet s/h at FPGA (#794) 2018-06-18 17:04:12 +08:00
Robert Jördens 6272052d15 ad9154: don't drive the bsm with txen pins 2018-06-18 10:04:42 +02:00
Robert Jördens 32484a62de sayma_amc: remove unused imports 2018-06-17 13:09:44 +02:00
Sebastien Bourdeauducq 4f0c918dd3 slave_fpga: improve messaging 2018-06-17 00:27:27 +08:00
Robert Jördens 53ab255c00 sayma_amc: enable slave fpga loading (#813) 2018-06-16 12:47:26 +02:00
Robert Jördens f9910ab242 i2c: support selecting multiple or no channels 
closes #1054
 2018-06-15 19:36:37 +02:00
Robert Jördens 40baa8ecba hmc7043: disable ch 10 and 11 group 2018-06-15 15:34:31 +00:00
Robert Jördens 70fd369e2f conda: bump migen (sayma lvds diff term) 2018-06-15 17:28:49 +02:00
Robert Jördens edfae3c4ba hmc7043: make fpga fabric clocks lvds 
2 V common and 1.9 Vpp swing
is brutal to the banks (HP 1.8V AMC and RT 1.8V RTM)
 2018-06-15 14:24:33 +00:00
Robert Jördens f385add8b1 slave_fpga: disable cclk and din drive when done 
to guard against accidental contention (old rtm gateware
but #813 rework done)
 2018-06-13 16:26:48 +00:00
Robert Jördens 1029ac870b sayma_rtm: don't drive txen pins 
pins disabled by config
necessary for using that pin as DIN (#813)
 2018-06-13 16:11:30 +00:00
Sebastien Bourdeauducq 68d16fc292 serwb: support single-ended signals 
Low-speed PHY only.
 2018-06-13 21:28:21 +08:00
Robert Jördens f8627952c8 conda: fix migen build string 2018-06-12 20:25:28 +02:00
Robert Jördens a9a25f2605 sayma_rtm: drive ref_lo_clk_sel, and set clk muxes early 2018-06-12 20:00:12 +02:00
Robert Jördens aff7fa008f Revert "artiq_flash/sayma: check for DONE after load" 
This reverts commit 2de5b0cf25.

would make artiq uninstallable on windows as win buildbot is broken
 2018-06-12 19:14:43 +02:00
Robert Jördens 2de5b0cf25 artiq_flash/sayma: check for DONE after load 2018-06-13 00:47:43 +08:00
Thomas Harty b90a8fcc82 Merge branch 'master' of https://github.com/m-labs/artiq 2018-06-12 14:55:22 +01:00
ion 28ecf81c6c Sayma: HMC7043 init and detect no longer need results. 2018-06-12 13:10:26 +01:00
ion c8935f7adf Sayma: bypass dividers where possible to minimize noise (nb this changes the output skew). 2018-06-12 12:56:04 +01:00
hartytp 7a0140ecb2
Sayma HMC830: update interface and register writes. (#1068) 
* Break the HMC830 init into separate functions for general purpose (but, integer-N) init, setting dividers and checking lock

* Use 1.6mA ICP (which the loop filter was optimized for)

* Go through the data sheet carefully and set all registers to the correct value (e.g. ensure that all settings are correctly optimized for integer-N usage)

* Change divider values (now using 100MHz PFD, which should give lower noise in theory)
 2018-06-12 12:37:17 +01:00
Robert Jördens a9d97101fc slave_fpga: add another check 2018-06-12 10:24:04 +02:00
Robert Jördens a143e238a8 savel_fpga: get rid of unneeded config 2018-06-12 10:24:04 +02:00
Robert Jördens 4912f53ab4 slave_fpga: board_misoc 2018-06-12 10:24:04 +02:00
hartytp cb6e44b23a Sayma: disable unused HMC7043 outputs. 2018-06-12 16:18:20 +08:00
Robert Jördens 0b086225a9 sawg: don't use Cat() for signed signals 
c.f. #1039 #1040 #1022 #1058 #1044
 2018-06-09 07:33:47 +00:00
Robert Jördens 5b73dd8604 sawg: accurate unittest rtio freq 2018-06-08 17:22:13 +02:00
Robert Jördens 6a7983cf89 conda: bump misoc 
closes #1039
closes #1040
closes #1022
closes #1058
closes #1044
 2018-06-08 17:11:01 +02:00
Robert Jördens 735e4e8561 pcu: spelling 2018-06-08 14:39:22 +00:00
Robert Jördens e5f6750171 sawg: cleanup double assign 2018-06-08 14:31:55 +00:00
Florent Kermarrec 53e9e475d0 serwb: transmit zeroes when nothing to transmit (for prbs), improve rx idle detection 2018-06-08 16:10:31 +02:00