slave_fpga: board_misoc

2018-06-09 20:03:22 +08:00 · 2018-06-09 20:03:22 +08:00 · 4912f53ab4
parent cb6e44b23a
commit 4912f53ab4
1 changed files with 1 additions and 1 deletions
--- a/artiq/firmware/libboard_artiq/slave_fpga.rs
+++ b/artiq/firmware/libboard_artiq/slave_fpga.rs
@ -1,4 +1,4 @@
-use board::{csr, clock};
+use board_misoc::{csr, clock};
 use core::slice;
 use byteorder::{ByteOrder, BigEndian};