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artiq
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Sayma: bypass dividers where possible to minimize noise (nb this changes the output skew).

new-openocd
ion 2018-06-12 12:56:04 +01:00
parent 7a0140ecb2
commit c8935f7adf
1 changed files with 5 additions and 2 deletions
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7
artiq/firmware/libboard_artiq/hmc830_7043.rs
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@ -288,8 +288,11 @@ pub mod hmc7043 {
write(channel_base + 0x3, aphase & 0x1f);
write(channel_base + 0x4, dphase & 0x1f);
// No analog phase shift on clock channels
if (channel % 2) == 0 { write(channel_base + 0x7, 0x00); }
// bypass analog phase shift on clock channels to reduce noise
if (channel % 2) == 0 {
if divider != 0 { write(channel_base + 0x7, 0x00); } // enable divider
else { write(channel_base + 0x7, 0x03); } // bypass divider for lowest noise
}
else { write(channel_base + 0x7, 0x01); }
write(channel_base + 0x8, 0x08)