M-Labs
/
artiq
mirror of https://github.com/m-labs/artiq.git
2
0
Fork 2
Code Issues Projects Releases Wiki Activity
6,344 Commits 13 Branches 35 Tags 25 MiB
Commit Graph

6344 Commits

Author SHA1 Message Date
Sebastien Bourdeauducq a3c5cdeb86 manual/drtio: update output internal description (SED, 'destination' switching terminology) 2018-11-26 18:36:59 +08:00
Robert Jördens cc61ee9139 urukul: work around windows numpy int peculiarity 
"OverflowError: Python int too large to convert to C long" otherwise

opticlock#74

Signed-off-by: Robert Jördens <rj@quartiq.de>
 2018-11-25 16:58:10 +01:00
Sebastien Bourdeauducq 74371399de RELEASE_NOTES: remove ARTIQ-5 entry 2018-11-20 18:39:27 +08:00
Sebastien Bourdeauducq bf50dcf76d conda: use misoc release 2018-11-20 17:15:53 +08:00
Sebastien Bourdeauducq 8f9858be4c ad9914: remove automatic continuous phase compensation (like Urukul) 2018-11-19 22:00:20 +08:00
Sebastien Bourdeauducq 22a223bf82 examples/master: clean up remnants of early urukul tests 2018-11-19 21:42:41 +08:00
Sebastien Bourdeauducq f5befba5c9 conda: bump misoc (attempt to WA conda problem) 2018-11-19 13:24:28 +08:00
Sebastien Bourdeauducq b5cdb1c1e0 try to work around conda problem 2018-11-18 22:32:17 +08:00
Sebastien Bourdeauducq a3e0b1c5b4 ad9914,spi2: add warnings about driver state and DMA. Closes #1113 2018-11-17 22:10:20 +08:00
Sebastien Bourdeauducq 78d4b3a7da gateware/targets: expose variant lists 
This allows writing scripts that build all variants.
 2018-11-17 22:10:20 +08:00
Sebastien Bourdeauducq 69e699c7bd ttl: compensate for SED latency in input gating 
Closes #1137
 2018-11-17 22:10:20 +08:00
Robert Jördens 3ad68f65c5 urukul: make get_att_mu() not alter state 
Signed-off-by: Robert Jördens <rj@quartiq.de>
 2018-11-16 14:56:26 +00:00
Robert Jördens d1eee7c0ea ad9910: ensure sync is driven when required 
close #1194

Signed-off-by: Robert Jördens <rj@quartiq.de>
 2018-11-16 13:21:01 +00:00
Sebastien Bourdeauducq de9d21ffc8 nix: use fetchFromGitHub for llvmlite 2018-11-16 15:14:20 +08:00
Sebastien Bourdeauducq d3483c1d26 kasli: fix SDRAM read delay reset/wrap issue. Closes #1149 2018-11-15 19:40:35 +08:00
Robert Jördens 494ffca4d3 gui,scan: add CenterScan Scannable variant 
* parametrized by center/span/step instead of
  start/stop/npoints which is more convenient in some applications
* no scan widget support so far

Signed-off-by: Robert Jördens <rj@quartiq.de>
 2018-11-15 13:30:43 +08:00
Robert Jördens f77a75ab17 test_ad9910: robustify w.r.t. profile synchronization 
Signed-off-by: Robert Jördens <rj@quartiq.de>
 2018-11-14 08:42:27 +01:00
Robert Jördens c3178c2cab ad9910: profile support 
Signed-off-by: Robert Jördens <rj@quartiq.de>
 2018-11-14 08:30:28 +01:00
Robert Jördens d0cadfeb4b ad9910: more idiomatic register names 
Signed-off-by: Robert Jördens <rj@quartiq.de>
 2018-11-14 07:55:01 +01:00
Robert Jördens a52d1be140 urukul: expose PROFILE setting 
* add documentation
* add unittest

Signed-off-by: Robert Jördens <rj@quartiq.de>
 2018-11-14 07:43:56 +01:00
Robert Jördens 2af6edb8f5 eem: fix reset/sync in suservo 
Signed-off-by: Robert Jördens <rj@quartiq.de>
 2018-11-13 13:00:54 +00:00
whitequark 248c1cf7dc firmware: fix another TOCTTOU race in sync/async RPC code. 2018-11-13 00:58:20 +08:00
whitequark 68aad3e482 firmware: fix TOCTTOU race in sync/async RPC code. 
Before this commit, the main loop in session code was laid like:

  1. process_kern_queued_rpc
  2. process_host_message
  3. process_kern_message

If a host message (such as an RPC reply) caused the kernel to exit,
then any async RPCs would not complete, since RunFinished immediately
shuts down the kernel.

Fix this by reordering 1 and 2.
 2018-11-13 00:57:09 +08:00
Robert Jördens a4997c56cf ad9910: simplify edge detection logic 
Signed-off-by: Robert Jördens <rj@quartiq.de>
 2018-11-09 18:54:34 +00:00
Robert Jördens e927551827 manual: add highfinesse-net port 2018-11-09 19:39:25 +01:00
Robert Jördens 14b6b63916 ad9910: rewire io_delay tuning 
This now reliably locates the SYNC_CLK-IO_UPDATE edge by doing two
scans at different delays between start and stop IO_UPDATE.
It also works well when one delay is very close to the edge.
And it correctly identifies which (start or stop) pulse hit or crossed
the SYNC_CLK edge.

for #1143

Signed-off-by: Robert Jördens <rj@quartiq.de>
 2018-11-09 18:38:27 +00:00
Robert Jördens fe3d6661eb manual: kasli device name for zadig on windows 
Signed-off-by: Robert Jördens <rj@quartiq.de>
 2018-11-09 15:00:59 +01:00
Robert Jördens 38c6878d49 urukul: mention min/max attenuation 
Signed-off-by: Robert Jördens <rj@quartiq.de>
 2018-11-09 13:32:05 +01:00
Robert Jördens e565ca6b82 urukul: slow down att write to datasheet limit 
Signed-off-by: Robert Jördens <rj@quartiq.de>
 2018-11-09 13:23:06 +01:00
Robert Jördens 998be50f07 urukul: handle MSB in att_reg 
Signed-off-by: Robert Jördens <rj@quartiq.de>
 2018-11-09 13:21:14 +01:00
David Nadlinger 9740032a94 firmware: Fix dma_record_output_wide 2018-11-08 11:06:43 +00:00
Robert Jördens fcb611d1d2 test_ad9910: don't expect large SYNC_IN delay margins 
sinara-hw/Urukul#16

Signed-off-by: Robert Jördens <rj@quartiq.de>
 2018-11-07 18:18:35 +01:00
Robert Jördens e6efe830c4 ad9910: rewire sync delay tuning 
* search from wide window end
* decouple margins and minimum window size
* add note about kasli jitter

Signed-off-by: Robert Jördens <rj@quartiq.de>
 2018-11-07 14:52:03 +00:00
Robert Jördens 6c00ab57c0 test_ad9910: relax SYNC window 
Signed-off-by: Robert Jördens <rj@quartiq.de>
 2018-11-06 19:31:38 +01:00
Robert Jördens 172633c7da test_ad9910: default to a useful seed 
Signed-off-by: Robert Jördens <rj@quartiq.de>
 2018-11-06 17:35:57 +01:00
Robert Jördens 0b2661a34d ad9910: robustify SYNC window finding 
don't integrate too long, find the window tip fast and early
a couple 100 SYNC pulses are sufficient

Signed-off-by: Robert Jördens <rj@quartiq.de>
 2018-11-06 12:41:21 +00:00
Robert Jördens ba4bf6e59b kasli: don't pass rtio pll feedback through bufg 
UG472: "The MMCM performance increases because the
feedback clock is not subjected to noise on the core supply since it
never passes through a block powered by this supply."

Signed-off-by: Robert Jördens <rj@quartiq.de>
 2018-11-06 11:58:55 +00:00
Robert Jördens b6e4961b0f kasli: lower RTIO clock jitter 
* high bandwidth since the si5324 is good
* no low power ibufgds
* drop bufg between ibufgds and pll
* increase pll vco frequency to 1.5 GHz

Signed-off-by: Robert Jördens <rj@quartiq.de>
 2018-11-06 11:43:19 +00:00
Robert Jördens e17e458c58 ptb2: add sync to urukul0 for ad9910 usage 
Signed-off-by: Robert Jördens <rj@quartiq.de>
 2018-11-06 10:06:51 +00:00
Robert Jördens 73b7124091 test_ad9910: print sync scan for debugging 
Signed-off-by: Robert Jördens <rj@quartiq.de>
 2018-11-06 10:04:21 +01:00
Sebastien Bourdeauducq 9a3d81ffee kasli: fix tester clk_sel 2018-11-06 14:49:21 +08:00
Sebastien Bourdeauducq fb12df7e01 Revert "kasli_tester: urukul0 mmcx clock defunct" 
This reverts commit 68220c316d.
 2018-11-06 14:33:21 +08:00
Robert Jördens 31f68ddf6c Merge branch 'urukul-sync' 
* urukul-sync: (29 commits)
  urukul: flake8 [nfc]
  ad9910: flake8 [nfc]
  urukul/ad9910 test: remove unused import
  test_urukul: relax speed
  urukul,ad9910: print speed metrics
  kasli: add PTB2 (external clock and SYNC)
  kasli: add sync to LUH, HUB, Opticlock
  kasli_tester: urukul0 mmcx clock defunct
  test_ad9910: relax ifc mode read
  tests: add Urukul-AD9910 HITL unittests including SYNC
  ad9910: add init bit explanation
  test: add Urukul CPLD HITL tests
  ad9910: fiducial timestamp for tracking phase mode
  ad9910: add phase modes
  ad9910: fix pll timeout loop
  tester: add urukul sync
  ptb: back out urukul-sync
  ad9910: add IO_UPDATE alignment and tuning
  urukul: set up sync_in generator
  ad9910: add io_update alignment measurement
  ...

close #1143
 2018-11-05 19:54:30 +01:00
Robert Jördens 6fb18270a2 urukul: flake8 [nfc] 
Signed-off-by: Robert Jördens <rj@quartiq.de>
 2018-11-05 19:45:24 +01:00
Robert Jördens 832690af9a ad9910: flake8 [nfc] 
Signed-off-by: Robert Jördens <rj@quartiq.de>
 2018-11-05 19:44:51 +01:00
Robert Jördens 6d525e2f9a urukul/ad9910 test: remove unused import 
Signed-off-by: Robert Jördens <rj@quartiq.de>
 2018-11-05 19:40:57 +01:00
Robert Jördens 36c5a7cd04 test_urukul: relax speed 
works fine at < 3µs here but needs <5 µs on buildbot-kasli-tester

Signed-off-by: Robert Jördens <rj@quartiq.de>
 2018-11-05 19:37:20 +01:00
Robert Jördens 89fecfab50 urukul,ad9910: print speed metrics 
Signed-off-by: Robert Jördens <rj@quartiq.de>
 2018-11-05 19:37:18 +01:00
Robert Jördens 32d538f72b kasli: add PTB2 (external clock and SYNC) 
Signed-off-by: Robert Jördens <rj@quartiq.de>
 2018-11-05 19:37:16 +01:00
Robert Jördens d8a5951a13 kasli: add sync to LUH, HUB, Opticlock 
for #1143, also add missing LUH device db

Signed-off-by: Robert Jördens <rj@quartiq.de>
 2018-11-05 19:37:14 +01:00