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test_ad9910: don't expect large SYNC_IN delay margins 

sinara-hw/Urukul#16

Signed-off-by: Robert Jördens <rj@quartiq.de>
pull/1191/head
Robert Jördens 2018-11-07 18:18:35 +01:00
parent e6efe830c4
commit fcb611d1d2
1 changed files with 3 additions and 1 deletions
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artiq/test/coredevice/test_ad9910.py
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@ -82,7 +82,9 @@ class AD9910Exp(EnvExperiment):
print(err)
self.core.break_realtime()
dly, win = self.dev.tune_sync_delay()
self.sync_scan(err, win=win + 1) # tighten window by 2*75ps
self.sync_scan(err, win=win)
# FIXME: win + 1 # tighten window by 2*75ps
# after https://github.com/sinara-hw/Urukul/issues/16
self.set_dataset("dly", dly)
self.set_dataset("win", win)
self.set_dataset("err", err)