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kasli: fix SDRAM read delay reset/wrap issue. Closes #1149

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This commit is contained in:
Sebastien Bourdeauducq 2018-11-15 19:40:35 +08:00
parent 494ffca4d3
commit d3483c1d26
2 changed files with 19 additions and 1 deletions
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18
artiq/firmware/libboard_misoc/sdram.rs
View File

@ -242,6 +242,12 @@ mod ddr {
ddrphy::dly_sel_write(1 << (DQS_SIGNAL_COUNT - n - 1));
ddrphy::rdly_dq_rst_write(1);
#[cfg(soc_platform = "kasli")]
{
for _ in 0..3 {
ddrphy::rdly_dq_bitslip_write(1);
}
}
for _ in 0..DDRPHY_MAX_DELAY {
let mut working = true;
@ -327,6 +333,12 @@ mod ddr {
let mut max_seen_valid = 0;
ddrphy::rdly_dq_rst_write(1);
#[cfg(soc_platform = "kasli")]
{
for _ in 0..3 {
ddrphy::rdly_dq_bitslip_write(1);
}
}
for delay in 0..DDRPHY_MAX_DELAY {
let mut valid = true;
@ -384,6 +396,12 @@ mod ddr {
// Set delay to the middle
ddrphy::rdly_dq_rst_write(1);
#[cfg(soc_platform = "kasli")]
{
for _ in 0..3 {
ddrphy::rdly_dq_bitslip_write(1);
}
}
for _ in 0..mean_delay {
ddrphy::rdly_dq_inc_write(1);
}

2
conda/artiq-dev/meta.yaml
View File

@ -15,7 +15,7 @@ requirements:
- python >=3.5.3,<3.6
- setuptools 33.1.1
- migen 0.8 py35_0+git2d62c0c
- misoc 0.11 py35_31+git5ce139dd
- misoc 0.11 py35_33+git128750aa
- jesd204b 0.10
- microscope
- binutils-or1k-linux >=2.27