mirror of https://github.com/m-labs/artiq.git
ad9910: rewire io_delay tuning
This now reliably locates the SYNC_CLK-IO_UPDATE edge by doing two scans at different delays between start and stop IO_UPDATE. It also works well when one delay is very close to the edge. And it correctly identifies which (start or stop) pulse hit or crossed the SYNC_CLK edge. for #1143 Signed-off-by: Robert Jördens <rj@quartiq.de>
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@ -466,17 +466,18 @@ class AD9910:
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raise ValueError("no valid window/delay")
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@kernel
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def measure_io_update_alignment(self, io_up_delay):
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def measure_io_update_alignment(self, delay_start, delay_stop):
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"""Use the digital ramp generator to locate the alignment between
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IO_UPDATE and SYNC_CLK.
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The ramp generator is set up to a linear frequency ramp
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(dFTW/t_SYNC_CLK=1) and started at a RTIO time stamp.
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(dFTW/t_SYNC_CLK=1) and started at a coarse RTIO time stamp plus
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`delay_start` and stopped at a coarse RTIO time stamp plus
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`delay_stop`.
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After scanning the alignment, an IO_UPDATE delay midway between two
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edges should be chosen.
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:return: odd/even SYNC_CLK cycle indicator
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:param delay_start: Start IO_UPDATE delay in machine units.
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:param delay_stop: Stop IO_UPDATE delay in machine units.
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:return: Odd/even SYNC_CLK cycle indicator.
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"""
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# set up DRG
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# DRG ACC autoclear and LRR on io update
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@ -489,14 +490,16 @@ class AD9910:
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self.write32(_AD9910_REG_DRAMPR, 0x00010000)
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# dFTW = 1, (work around negative slope)
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self.write64(_AD9910_REG_DRAMPS, -1, 0)
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at_mu(now_mu() + 0x10 & ~0xf) # align to RTIO/2
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self.cpld.io_update.pulse_mu(8)
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# delay io_update after RTIO/2 edge
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t = now_mu() + 0x10 & ~0xf
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at_mu(t + delay_start)
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self.cpld.io_update.pulse_mu(32 - delay_start) # realign
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# disable DRG autoclear and LRR on io_update
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self.write32(_AD9910_REG_CFR1, 0x00000002)
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# stop DRG
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self.write64(_AD9910_REG_DRAMPS, 0, 0)
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at_mu((now_mu() + 0x10 & ~0xf) + io_up_delay) # delay
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self.cpld.io_update.pulse_mu(32 - io_up_delay) # realign
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at_mu(t + 0x1000 + delay_stop)
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self.cpld.io_update.pulse_mu(32 - delay_stop) # realign
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ftw = self.read32(_AD9910_REG_FTW) # read out effective FTW
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delay(100*us) # slack
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# disable DRG
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@ -510,22 +513,36 @@ class AD9910:
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Scan through increasing IO_UPDATE delays until a delay is found that
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lets IO_UPDATE be registered in the next SYNC_CLK cycle. Return a
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IO_UPDATE delay that is midway between two such SYNC_CLK transitions.
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IO_UPDATE delay that is as far away from that SYNC_CLK edge
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as possible.
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This method assumes that the IO_UPDATE TTLOut device has one machine
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unit resolution (SERDES) and that the ratio between fine RTIO frequency
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(RTIO time machine units) and SYNC_CLK is 4.
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unit resolution (SERDES).
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:return: Stable IO_UPDATE delay to be passed to the constructor
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:class:`AD9910` via the device database.
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"""
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period = 4 # f_RTIO/f_SYNC = 4
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max_delay = 8 # mu, 1 ns
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d0 = self.io_update_delay
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t0 = int32(self.measure_io_update_alignment(d0))
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for i in range(max_delay - 1):
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t = self.measure_io_update_alignment(
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(d0 + i + 1) & (max_delay - 1))
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if t != t0:
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return (d0 + i + period//2) & (period - 1)
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period = self.sysclk_per_mu * 4 # SYNC_CLK period
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repeat = 100
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for i in range(period):
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t = 0
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# check whether the sync edge is strictly between i, i+2
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for j in range(repeat):
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t += self.measure_io_update_alignment(i, i + 2)
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if t != 0: # no certain edge
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continue
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# check left/right half: i,i+1 and i+1,i+2
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t1 = [0, 0]
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for j in range(repeat):
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t1[0] += self.measure_io_update_alignment(i, i + 1)
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t1[1] += self.measure_io_update_alignment(i + 1, i + 2)
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if ((t1[0] == 0 and t1[1] == repeat) or # edge left of i + 1
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(t1[0] == repeat and t1[1] == 0) or # edge right of i + 1
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(t1[0] != 0 and t1[1] != 0 and # edge very close to i + 1
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t1[0] != repeat and t1[1] != repeat)):
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# the good delay is period//2 after the edge
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return (i + 1 + period//2) & (period - 1)
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else: # can't interpret result
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raise ValueError(
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"no clear IO_UPDATE-SYNC_CLK alignment edge found")
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raise ValueError("no IO_UPDATE-SYNC_CLK alignment edge found")
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@ -104,18 +104,21 @@ class AD9910Exp(EnvExperiment):
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self.core.break_realtime()
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self.dev.cpld.init()
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self.dev.init()
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bins = [0]*8
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self.scan_io_delay(bins)
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self.set_dataset("bins", bins)
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self.set_dataset("dly", self.dev.io_update_delay)
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bins1 = [0]*4
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bins2 = [0]*4
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self.scan_io_delay(bins1, bins2)
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self.set_dataset("bins1", bins1)
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self.set_dataset("bins2", bins2)
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self.set_dataset("dly", self.dev.tune_io_update_delay())
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@kernel
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def scan_io_delay(self, bins):
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def scan_io_delay(self, bins1, bins2):
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delay(100*us)
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n = 100
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for i in range(n):
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for phase in range(len(bins)):
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bins[phase] += self.dev.measure_io_update_alignment(phase)
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for j in range(len(bins1)):
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bins1[j] += self.dev.measure_io_update_alignment(j, j + 1)
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bins2[j] += self.dev.measure_io_update_alignment(j, j + 2)
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delay(10*ms)
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@kernel
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@ -174,12 +177,14 @@ class AD9910Test(ExperimentCase):
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def test_io_update_delay(self):
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self.execute(AD9910Exp, "io_update_delay")
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dly = self.dataset_mgr.get("dly")
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bins = self.dataset_mgr.get("bins")
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print(dly, bins)
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n = max(bins)
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# test for 4-periodicity (SYNC_CLK) and maximal contrast
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for i in range(len(bins)):
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self.assertEqual(abs(bins[i] - bins[(i + 4) % 8]), n)
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bins1 = self.dataset_mgr.get("bins1")
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bins2 = self.dataset_mgr.get("bins2")
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print(dly, bins1, bins2)
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n = max(bins2)
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# no edge at optimal delay
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self.assertEqual(bins2[(dly + 1) & 3], 0)
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# edge at expected position
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self.assertEqual(bins2[(dly + 3) & 3], n)
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def test_sw_readback(self):
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self.execute(AD9910Exp, "sw_readback")
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