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7232 Commits

Author SHA1 Message Date
Sebastien Bourdeauducq 98cd9a539c compiler: support Cortex A9 target 2019-08-26 10:46:22 +08:00
Astro afe162ceca firmware: don't unwrap() but propagate pca9548 errors 2019-08-17 09:15:26 +08:00
Astro a8aabd3815 firwmare: turn i2c errors into &str 2019-08-17 09:15:26 +08:00
Astro 8fc5ce902f firmware: let kasli obtain default hardware_addr from i2c_eeprom 2019-08-17 09:15:26 +08:00
Astro d666f3d573 firmware: factor out mod pca9548 from si5324 
orepares for further i2c devices.
 2019-08-17 09:15:26 +08:00
Sebastien Bourdeauducq 1fd2322662 wrpll/thls: implement global writeback 2019-08-15 23:16:17 +08:00
Sebastien Bourdeauducq 24082b687e wrpll/filters: clean up and make compatible with thls 2019-08-15 17:58:22 +08:00
Sebastien Bourdeauducq 9331fafab0 wrpll/filters: new code from Weida 2019-08-15 17:24:40 +08:00
Sebastien Bourdeauducq 5c3974c265 wrpll/thls: fix opcode decoding 2019-08-15 17:12:48 +08:00
Sebastien Bourdeauducq 19620948bf wrpll/thls: implement signed numbers 2019-08-15 17:04:17 +08:00
Sebastien Bourdeauducq efc43142a6 wrpll/thls: implement min/max 2019-08-15 16:42:59 +08:00
Sebastien Bourdeauducq 44969b03ad wrpll/thls: rework instruction decoding 2019-08-15 15:55:13 +08:00
Sebastien Bourdeauducq 2776c5b16b wrpll/thls: support mulshift 2019-08-15 15:07:13 +08:00
Robert Jördens e9b78b62db kasli_tester/zotino: always alternate voltage sign 
Before the voltages on a second Zotino would start 2.1, 1.9, 2.2, 1.8
..., 3.6, 0.4 and overlap with the voltages on the first.
Now the voltages are 2.1, -2.1, 2.2, -2.2, ..., 3.6, -3.6 which allows
quick identification of card/channel and easy prediction when deploying.
 2019-08-06 17:38:55 +02:00
Sebastien Bourdeauducq 5f8acb3f96 manual: fix location of shell-dev.nix (#1346) 2019-08-05 13:34:35 +08:00
Sebastien Bourdeauducq f861459ace wrpll: add filter algorithms (WIP) 2019-08-02 13:23:16 +08:00
David Nadlinger 99e490f9ff coredevice/suservo: Slightly reword get_adc[_mu]() docstring for clarity 
This hopefully suggests a bit better that the value is the last one
fetched by the servo (i.e. needs the servo active to update), rather
than somehow requesting a new sample to be taken.
 2019-07-30 12:22:08 +01:00
David Nadlinger 4446ebf9ca README: Fix link to manual 2019-07-30 11:28:12 +01:00
Robert Jördens 3f0657f2a8 artiq_influxdb_schedule: add schedule logger 
Signed-off-by: Robert Jördens <rj@quartiq.de>
 2019-07-26 14:47:18 +02:00
Sebastien Bourdeauducq 7a5dcbe60e wrpll/thls: support processor start/stop 2019-07-24 18:51:33 +08:00
Sebastien Bourdeauducq b8870997d0 doc: clarify TTL direction control with buffered cards 2019-07-24 10:04:45 +08:00
Sebastien Bourdeauducq 623446f82c wrpll/thls: simple simulation demo 2019-07-20 18:50:57 +08:00
Sebastien Bourdeauducq 831b3514d3 wrpll/thls: stop at return statement 2019-07-19 16:27:29 +08:00
Sebastien Bourdeauducq 930291f606 update conda channel URL 2019-07-19 16:11:03 +08:00
Sebastien Bourdeauducq e95b7b9d4b manual: fix typos 2019-07-18 09:30:21 +08:00
Sebastien Bourdeauducq 75e8d54c27 install-with-conda: remove unnecessary import 2019-07-18 00:52:31 +08:00
Sebastien Bourdeauducq 2ffc843790 update installation instructions 2019-07-18 00:51:47 +08:00
David Nadlinger 280915d54f coredevice/suservo: Adjust T_CYCLE to match gateware 
See GitHub #1338.
 2019-07-17 00:20:22 +01:00
Sebastien Bourdeauducq 34222b3f38 wrpll: encode thls program 2019-07-09 17:56:14 +08:00
Sebastien Bourdeauducq 5f461d08cd wrpll: add simple thls compiler 2019-07-09 16:07:31 +08:00
Robert Jördens f7e10759dc suservo: note requirement to stop servo when accessing state 
As already mentioned in the gateware.

One alternative would be to detect address collisions and
stall the read for one cycle.

Note that there will in general not be a consistent view of the servo
state unless the servo is stopped.

close #1337
 2019-07-08 18:37:42 +02:00
Sebastien Bourdeauducq e4fff390a8 si590 -> si549 
Had mistaken the part numbers.
 2019-07-07 09:39:55 +08:00
Sebastien Bourdeauducq dceb5ae501 wrpll: Si590 I2C mux, CDC 2019-07-05 23:42:37 +08:00
Sebastien Bourdeauducq f8dba7ae35 rtio: use BlindTransfer from Migen 2019-07-05 18:46:18 +08:00
Robert Jördens 4d01410ce5 install-with-conda: notes on proxy 2019-07-04 14:04:32 +02:00
Robert Jördens 8407c526e8 install-with-conda: de-prioritize conda-forge 2019-07-04 11:19:55 +02:00
Sebastien Bourdeauducq 5a9bb0ecba runtime: fix incorrect 'RTIO clock failed' report 2019-06-24 23:33:13 +08:00
David Nadlinger 8bf9640185 coredevice/suservo: Fix output IIR state width in docstring 2019-06-21 11:27:39 +02:00
David Nadlinger 34f48f57cc coredevice/suservo: Fix {get,set}_y_mu() scaling 
Previously, Channel.set_y(1) would set the output to -1 instead.
 2019-06-21 11:27:39 +02:00
Sebastien Bourdeauducq f6edceb23d kasli_tester: cleanup/fix test skipping 2019-06-21 16:00:14 +08:00
whitequark b8b9fa51bd libdyld: accept objects with no rela relocations. 2019-06-17 06:43:34 +00:00
David Nadlinger 0353966ef7 gateware/suservo: Sign-extend data on RTIO read-back 
See GitHub #1327 for original patch by Brad Bondurant.
 2019-06-14 23:46:16 +01:00
David Nadlinger 720838a23e gateware/suservo: Avoid magic number for activation delay width 
Mostly for documentation purposes; 8 bits ought to be enough for
everyone.
 2019-06-14 23:45:40 +01:00
Robert Jördens 53789ba9aa tester: handle urukul switch differences 2019-06-14 10:54:00 +00:00
Robert Jördens 6655e567df ddb_template: urukul fixes 
* fix/add sw (ad9912 and ad9910)
* allow pll_n to be changed
 2019-06-14 10:53:03 +00:00
Sebastien Bourdeauducq 53c778ae2d runtime: fix previous commit 2019-06-14 15:53:01 +08:00
Sebastien Bourdeauducq a947867887 runtime: support Kasli Si5324 bypass via rtio_clock=e 2019-06-14 15:48:05 +08:00
Sebastien Bourdeauducq 66a66b03b4 style 2019-06-14 15:29:16 +08:00
Sebastien Bourdeauducq 87ce24e867 runtime: refactor startup and RTIO clocking initialization 2019-06-14 15:26:30 +08:00
Sebastien Bourdeauducq 43e58c939c sayma: drop MasterDAC 
This seemed like a good idea then, but it introduces complexity, corner cases, and additional testing difficulties.

Now Sayma works fine with Kasli as a master, which is simpler.
 2019-06-14 14:06:16 +08:00