292a07d830
doc: EBAZ4205 SD Boot
2024-11-16 17:39:26 +08:00
56bd975a34
doc: Typo
2024-10-25 10:32:27 +08:00
newell
30b9479437
add AD9834 core device driver ( #2596 )
2024-10-17 14:14:45 +08:00
newell
700812471c
doc: Additonal EBAZ4205 documentation, fix JSON description terminology ( #2588 )
2024-10-16 14:12:40 +08:00
b751e5455b
ebaz4205 docs
2024-10-07 10:55:44 +08:00
e38dc59656
doc: Add ZC706 to core device page
2024-08-22 13:52:16 +08:00
c0805b9cb9
doc: Minor link fixes
2024-08-12 16:52:45 +08:00
61ac6da547
doc: Add references to command line tools
2024-07-29 13:40:11 +08:00
architeuthidae
6698a6f80c
doc: Building + developing rewrite ( #2496 )
...
Co-authored-by: architeuthidae <am@m-labs.hk>
2024-07-27 22:14:25 +08:00
b0d2705c38
doc: link fixes
2024-07-19 18:35:21 +08:00
7e6a94c6b0
doc: Trailing spaces
2024-07-19 18:17:40 +08:00
architeuthidae
5aee0df9f0
doc: Split installing page ( #2495 )
...
Co-authored-by: architeuthidae <am@m-labs.hk>
2024-07-19 17:46:05 +08:00
architeuthidae
499eb42c3e
doc: Edit of manual reference pages ( #2466 )
...
Co-authored-by: architeuthis <am@m-labs.hk>
2024-07-18 17:53:34 +08:00
0e1b29c5d9
doc: Assorted typos and dead links
2024-07-17 11:36:59 +08:00
architeuthidae
f432529014
doc: 'Core device' manual page overhaul ( #2430 )
2024-06-12 14:50:48 +08:00
architeuthis
8b64315ecf
Deleted reference to board packages
2024-06-06 13:44:04 +08:00
architeuthis
4509ad86f8
Remove outdated references to examples/master, fix labels
2024-06-06 13:44:04 +08:00
architeuthis
59302da71c
docs: 'Installing ARTIQ' manual page overhaul
2024-06-06 13:44:04 +08:00
d0b8818688
Add 125 MHz from 80 MHz reference option to rtio clocking
...
Signed-off-by: Egor Savkin <es@m-labs.hk>
2023-04-13 14:57:24 +08:00
ciciwu
67ca48fa84
manual: fix formatting ( #1865 )
2022-03-08 19:03:47 +08:00
9b1d7e297d
runtime: clock input specification improvements
...
closes #1735
2021-10-28 16:21:51 +08:00
1e869aedd3
docs: clarify rtio_clock=e req's and use case
...
This regularly leads to people misunderstanding the setting.
Mentioning the Si5324 specifically or Urukul synchronization doesn't help constraining or explaining the feature, its consequences and requirements.
Despite being non-standard this feature is also generally not sufficient to achieve cross-device determinism as the other devices need to be made deterministic as well.
2021-08-03 11:36:04 +02:00
a947867887
runtime: support Kasli Si5324 bypass via rtio_clock=e
2019-06-14 15:48:05 +08:00
7e7f463d11
manual: fix fs.com link
2019-05-07 22:19:23 +08:00
4e230bb768
manual: update core device section on Kasli
2019-05-07 20:19:13 +08:00
766d87f626
doc: artiq_coreconfig → artiq_coremgmt config. Closes #1111
2018-07-20 11:59:07 +08:00
3168b193e6
kc705: remove Zotino and Urukul
...
* use Kasli instead for using EEMs
* code required outdated VHDCI adapter 1.0
2018-07-17 17:48:57 +08:00
b10d3ee4b4
make RTIO clock switch optional and simplify
...
Kasli no longer has an internal RTIO clock.
Switching clocks dynamically is no longer supported.
2018-05-18 17:41:34 +08:00
7986391422
manual: update Kasli section
2018-02-21 12:04:14 +08:00
6c4681e7d2
manual: fix minor errors
2018-02-21 11:57:57 +08:00
21cd24fe80
manual: add section on Kasli/opticlock
2018-01-15 15:13:24 +01:00
94b84ebe7c
kc705_dds: add urukul spi/ttl channels
2018-01-02 13:20:48 +01:00
569484f888
remove phaser, adapt SAWG example to Sayma
2017-12-14 18:49:27 +08:00
b89929565c
manual: fix formatting problem
2017-11-25 14:46:31 +08:00
33d339947c
doc: add information on how to connect Zotino
2017-11-01 20:20:42 +08:00
d80cf8d59d
kc705: add TTLs and shift register driver for FMC DIO
2017-10-31 23:14:39 +08:00
5803ac9998
gateware: add Zotino SPI to NIST CLOCK target
2017-10-23 15:04:30 +08:00
43d551f1d8
README_PHASER: integrate into board port docs
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* rewrite setup commands for usage of artiq-dev metapackage
* integrate with rest of installation documentation
* move contents of README_PHASER to core_device.rst
* closes #815
2017-08-29 16:15:51 +02:00
94ee48860a
doc: fix phaser channel number statement
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closes #781
2017-07-15 20:24:50 +02:00
mntng
40ca951750
kc705: add SPI bus for memory card
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This will be useful for SPI unit tests using a SD card as victim.
2017-07-12 00:27:44 +08:00
9ab63920e0
Remove Pipistrello support
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Closes #658
Closes #381
2017-05-15 17:17:44 +08:00
f7e8961ab0
Merge branch 'master' into phaser
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* master: (23 commits)
RELEASE_NOTES: update
pipistrello: add some inputs
Remove last vestiges of nist_qc1.
Fully drop AD9858 and kc705-nist_qc1 support (closes #576 ).
coredevice.dds: reimplement fully in ARTIQ Python.
compiler: unbreak casts to int32/int64.
analyses.constness: fix false positive on x[...].
inferencer: significantly improve the op-assignment diagnostic.
Fix tests.
Move mu_to_seconds, seconds_to_mu to Core.
artiq_devtool: don't crash on invalid utf-8.
artiq_devtool: detect a race condition during connect.
llvm_ir_generator: handle no-op coercions.
conda: use development version of migen/misoc
Revert accidentally committed code.
Revert "gateware: increase RTIO FIFO sizes for NIST_CLOCK. Closes #623 "
analyses.invariant_detection: implement (#622 ).
Fix whitespace.
coredevice.dds: work around the round(numpy.float64()) snafu.
coredevice.dds: update from obsolete int(width=) syntax (fixes #621 ).
...
2016-11-21 17:29:39 +01:00
93c310dfa5
pipistrello: add some inputs
2016-11-21 23:43:41 +08:00
whitequark
6aa5d9f6c6
Remove last vestiges of nist_qc1.
2016-11-21 15:36:22 +00:00
whitequark
5e8888d5f3
Fully drop AD9858 and kc705-nist_qc1 support ( closes #576 ).
2016-11-21 15:14:17 +00:00
18d18b6685
phaser: add sync ttl input for monitoring
2016-10-10 17:13:23 +02:00
4d87f0e9e0
phaser: instantiate jesd204b core, wire up
2016-10-06 14:44:22 +02:00
c54b6e2f3c
phaser: add README
2016-10-05 19:24:34 +02:00
4a0eaf0f95
phaser: add jesd204b rtio dds
...
gateware: add jesd204b awg
gateware: copy phaser (df3825a)
dsp/tools: update satadd mixin
phaser: no DDS stubs
dsp: accu fix
phaser: cleanup/reduce
sawg: kernel support and docs
sawg: coredevice api fixes
sawg: example ddb/experiment
phaser: add conda package
examples/phaser: typo
sawg: adapt tests, fix accu stb
sawg: tweak dds parameters
sawg: move/adapt/extend tests
sawg: test phy, refactor
phaser: non-rtio spi
phaser: target cli update
phaser: ad9154-fmc-ebz pins
phaser: reorganize fmc signal naming
phaser: add test mode stubs
phaser: txen is LVTTL
phaser: clk spi xfer test
phaser: spi for ad9154 and ad9516
phaser: spi tweaks
ad9154: add register map from ad9144.xml
ad9516: add register map from ad9517.xml and manual adaptation
ad9154_reg: just generate getter/setter macros as well
ad9154: reg WIP
ad9154: check and fix registers
kc705: single ended rtio_external_clk
use single ended user_sma_clk_n instead of p/n to free up one clock sma
kc705: mirror clk200 at user_sma_clock_p
ad9516_regs.h: fix B_COUNTER_MSB
phase: wire up clocking differently
needs patched misoc
kc705: feed rtio_external_clock directly
kc705: remove rtio_external_clk for phaser
phaser: spi tweaks
ad9516: some startup
ad9516_reg fixes
phaser: setup ad9516 for supposed 500 MHz operation
ad9516: use full duplex spi
ad9154_reg: add CONFIG_REG_2
ad9154_reg: fixes
phaser: write some ad9154 config
ad9154_reg: fixes
ad9154: more init, and human readable setup
ad9154/ad9516: merge spi support
ad9154: status readout
Revert "kc705: remove rtio_external_clk for phaser"
This reverts commit d500288bb44f2bf2eeb0c2f237aa207b0a8b1366.
Revert "kc705: feed rtio_external_clock directly"
This reverts commit 8dc7825519e3e75b7d3d29c9abf10fc6e3a8b4c5.
Revert "phase: wire up clocking differently"
This reverts commit ad9cc450ffa35abb54b0842d56f6cf6c53c6fbcc.
Revert "kc705: mirror clk200 at user_sma_clock_p"
This reverts commit 7f0dffdcdd28e648af84725682f82ec6e5642eba.
Revert "kc705: single ended rtio_external_clk"
This reverts commit a9426d983fbf5c1cb768da8f1da26d9b7335e9cf.
ad9516: 2000 MHz clock
phaser: test clock dist
phaser: test freqs
ad9154: iostandards
phaser: drop clock monitor
phaser: no separate i2c
phaser: drive rtio from refclk, wire up sysref
phaser: ttl channel for sync
ad9154: 4x interp, status, tweaks
phaser: sync/sysref 33V banks
phaser: sync/sysref LVDS_25 inputs are VCCO tolerant
phaser: user input-only ttls
phaser: rtio fully from refclk
ad9154: reg name usage fix
ad9154: check register modifications
Revert "ad9154: check register modifications"
This reverts commit 45121d90edf89f7bd8703503f9f317ad050f9564.
ad9154: fix status code
ad9154: addrinc, recal serdes pll
phaser: coredevice, example tweaks
sawg: missing import
sawg: type fixes
ad9514: move setup functions
ad9154: msb first also decreasing addr
phaser: use sys4x for rtio internal ref
phaser: move init code to main
phaser: naming cleanup
phaser: cleanup pins
phaser: move spi to kernel cpu
phaser: kernel support for ad9154 spi
ad9154: add r/w methods
ad9154: need return annotations
ad9154: r/w methods are kernels
ad9154_reg: portable helpers
phaser: cleanup startup kernel
ad9154: status test
ad9154: prbs test
ad9154: move setup, document
phaser: more documentation
2016-10-05 16:17:50 +02:00
4ef5eb2644
doc: move VADJ, closes #554
2016-09-09 18:40:58 +08:00
