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add AD9834 core device driver (#2596)
This commit is contained in:
newell
GitHub
parent
700812471c
commit
30b9479437
@ -20,6 +20,7 @@ ARTIQ-9 (Unreleased)
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* Compiler can now give automatic suggestions for ``kernel_invariants``.
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* Idle kernels now restart when written with ``artiq_coremgmt`` and stop when erased/removed from config.
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* New support for the EBAZ4205 Zynq-SoC control card.
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* New core device driver for the AD9834 DDS, tested with the ZonRi Technology Co., Ltd. AD9834-Module.
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ARTIQ-8
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-------
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397
artiq/coredevice/ad9834.py
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397
artiq/coredevice/ad9834.py
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@ -0,0 +1,397 @@
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"""
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RTIO Driver for the Analog Devices AD9834 DDS via 3-wire SPI interface.
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"""
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# https://www.analog.com/media/en/technical-documentation/data-sheets/AD9834.pdf
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# https://www.analog.com/media/en/technical-documentation/app-notes/an-1070.pdf
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from artiq.coredevice import spi2 as spi
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from artiq.experiment import *
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from artiq.language.core import *
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from artiq.language.types import *
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from artiq.language.units import *
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AD9834_B28 = 1 << 13
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AD9834_HLB = 1 << 12
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AD9834_FSEL = 1 << 11
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AD9834_PSEL = 1 << 10
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AD9834_PIN_SW = 1 << 9
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AD9834_RESET = 1 << 8
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AD9834_SLEEP1 = 1 << 7
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AD9834_SLEEP12 = 1 << 6
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AD9834_OPBITEN = 1 << 5
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AD9834_SIGN_PIB = 1 << 4
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AD9834_DIV2 = 1 << 3
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AD9834_MODE = 1 << 1
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AD9834_FREQ_REG_0 = 0b01 << 14
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AD9834_FREQ_REG_1 = 0b10 << 14
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FREQ_REGS = [AD9834_FREQ_REG_0, AD9834_FREQ_REG_1]
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AD9834_PHASE_REG = 0b11 << 14
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AD9834_PHASE_REG_0 = AD9834_PHASE_REG | (0 << 13)
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AD9834_PHASE_REG_1 = AD9834_PHASE_REG | (1 << 13)
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PHASE_REGS = [AD9834_PHASE_REG_0, AD9834_PHASE_REG_1]
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class AD9834:
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"""
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AD9834 DDS driver.
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This class provides control for the DDS AD9834.
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The driver utilizes bit-controlled :const:`AD9834_FSEL`, :const:`AD9834_PSEL`, and
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:const:`AD9834_RESET`. To pin control ``FSELECT``, ``PSELECT``, and ``RESET`` set
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:const:`AD9834_PIN_SW`. The ``ctrl_reg`` attribute is used to maintain the state of
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the control register, enabling persistent management of various configurations.
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:param spi_device: SPI bus device name.
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:param spi_freq: SPI bus clock frequency (default: 10 MHz, max: 40 MHz).
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:param clk_freq: DDS clock frequency (default: 75 MHz).
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:param core_device: Core device name (default: "core").
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"""
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kernel_invariants = {"core", "bus", "spi_freq", "clk_freq"}
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def __init__(
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self, dmgr, spi_device, spi_freq=10 * MHz, clk_freq=75 * MHz, core_device="core"
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):
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self.core = dmgr.get(core_device)
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self.bus = dmgr.get(spi_device)
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assert spi_freq <= 40 * MHz, "SPI frequency exceeds maximum value of 40 MHz"
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self.spi_freq = spi_freq
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self.clk_freq = clk_freq
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self.ctrl_reg = 0x0000 # Reset control register
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@kernel
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def init(self):
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"""
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Initialize the AD9834: configure the SPI bus and reset the DDS.
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This method performs the necessary setup for the AD9834 device, including:
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- Configuring the SPI bus parameters (clock polarity, data width, and frequency).
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- Putting the AD9834 into a reset state to ensure proper initialization.
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The SPI bus is configured to use 16 bits of data width with the clock frequency
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provided as a parameter when creating the AD9834 instance. After configuring
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the SPI bus, the method invokes :meth:`enable_reset()` to reset the AD9834.
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This is an essential step to prepare the device for subsequent configuration
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of frequency and phase.
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This method should be called before any other operations are performed
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on the AD9834 to ensure that the device is in a known state.
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"""
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self.bus.set_config(spi.SPI_CLK_POLARITY | spi.SPI_END, 16, self.spi_freq, 1)
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self.enable_reset()
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@kernel
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def set_frequency_reg(self, freq_reg, frequency: TFloat):
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"""
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Set the frequency for the specified frequency register.
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This method calculates the frequency word based on the provided frequency in Hz
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and writes it to the specified frequency register.
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:param freq_reg: The frequency register to write to, must be one of
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:const:`AD9834_FREQ_REG_0` or :const:`AD9834_FREQ_REG_1`.
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:param frequency: The desired frequency in Hz, which will be converted to a
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frequency word suitable for the AD9834.
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The frequency word is calculated using the formula:
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``freq_word = (frequency * (1 << 28)) / clk_freq``
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The result is limited to the lower 28 bits for compatibility with the AD9834.
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The method first sets the control register to enable the appropriate settings,
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then sends the fourteen least significant bits LSBs and fourteen most significant
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bits MSBs in two consecutive writes to the specified frequency register.
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"""
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if freq_reg not in FREQ_REGS:
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raise ValueError("Invalid frequency register")
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assert frequency <= 37.5 * MHz, "Frequency exceeds maximum value of 37.5 MHz"
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freq_word = int((frequency * (1 << 28)) / self.clk_freq) & 0x0FFFFFFF
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self.ctrl_reg |= AD9834_B28
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self.write(self.ctrl_reg)
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lsb = freq_word & 0x3FFF
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msb = (freq_word >> 14) & 0x3FFF
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self.write(freq_reg | lsb)
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self.write(freq_reg | msb)
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@kernel
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def set_frequency_reg_msb(self, freq_reg, word: TInt32):
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"""
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Set the fourteen most significant bits MSBs of the specified frequency register.
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This method updates the specified frequency register with the provided MSB value.
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It configures the control register to indicate that the MSB is being set.
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:param freq_reg: The frequency register to update, must be one of
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:const:`AD9834_FREQ_REG_0` or :const:`AD9834_FREQ_REG_1`.
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:param word: The value to be written to the fourteen MSBs of the frequency register.
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The method first clears the appropriate control bits, sets :const:`AD9834_HLB` to
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indicate that the MSB is being sent, and then writes the updated control register
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followed by the MSB value to the specified frequency register.
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"""
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if freq_reg not in FREQ_REGS:
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raise ValueError("Invalid frequency register")
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self.ctrl_reg &= ~AD9834_B28
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self.ctrl_reg |= AD9834_HLB
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self.write(self.ctrl_reg)
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self.write(freq_reg | (word & 0x3FFF))
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@kernel
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def set_frequency_reg_lsb(self, freq_reg, word: TInt32):
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"""
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Set the fourteen least significant bits LSBs of the specified frequency register.
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This method updates the specified frequency register with the provided LSB value.
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It configures the control register to indicate that the LSB is being set.
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:param freq_reg: The frequency register to update, must be one of
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:const:`AD9834_FREQ_REG_0` or :const:`AD9834_FREQ_REG_1`.
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:param word: The value to be written to the fourteen LSBs of the frequency register.
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The method first clears the appropriate control bits and writes the updated control
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register followed by the LSB value to the specified frequency register.
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"""
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if freq_reg not in FREQ_REGS:
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raise ValueError("Invalid frequency register")
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self.ctrl_reg &= ~AD9834_B28
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self.ctrl_reg &= ~AD9834_HLB
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self.write(self.ctrl_reg)
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self.write(freq_reg | (word & 0x3FFF))
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@kernel
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def select_frequency_reg(self, freq_reg):
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"""
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Select the active frequency register for the phase accumulator.
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This method chooses between the two available frequency registers in the AD9834 to
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control the frequency of the output waveform. The control register is updated
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to reflect the selected frequency register.
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:param freq_reg: The frequency register to select. Must be one of
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:const:`AD9834_FREQ_REG_0` or :const:`AD9834_FREQ_REG_1`.
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"""
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if freq_reg not in FREQ_REGS:
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raise ValueError("Invalid frequency register")
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if freq_reg == FREQ_REGS[0]:
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self.ctrl_reg &= ~AD9834_FSEL
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else:
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self.ctrl_reg |= AD9834_FSEL
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self.ctrl_reg &= ~AD9834_PIN_SW
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self.write(self.ctrl_reg)
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@kernel
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def set_phase_reg(self, phase_reg, phase: TInt32):
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"""
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Set the phase for the specified phase register.
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This method updates the specified phase register with the provided phase value.
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:param phase_reg: The phase register to update, must be one of
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:const:`AD9834_PHASE_REG_0` or :const:`AD9834_PHASE_REG_1`.
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:param phase: The value to be written to the phase register.
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The method masks the phase value to ensure it fits within the 12-bit limit
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and writes it to the specified phase register.
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"""
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if phase_reg not in PHASE_REGS:
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raise ValueError("Invalid phase register")
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phase_word = phase & 0x0FFF
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self.write(phase_reg | phase_word)
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@kernel
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def select_phase_reg(self, phase_reg):
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"""
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Select the active phase register for the phase accumulator.
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This method chooses between the two available phase registers in the AD9834 to
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control the phase of the output waveform. The control register is updated
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to reflect the selected phase register.
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:param phase_reg: The phase register to select. Must be one of
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:const:`AD9834_PHASE_REG_0` or :const:`AD9834_PHASE_REG_1`.
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"""
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if phase_reg not in PHASE_REGS:
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raise ValueError("Invalid phase register")
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if phase_reg == PHASE_REGS[0]:
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self.ctrl_reg &= ~AD9834_PSEL
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else:
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self.ctrl_reg |= AD9834_PSEL
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self.ctrl_reg &= ~AD9834_PIN_SW
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self.write(self.ctrl_reg)
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@kernel
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def enable_reset(self):
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"""
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Enable the DDS reset.
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This method sets :const:`AD9834_RESET`, putting the AD9834 into a reset state.
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While in this state, the digital-to-analog converter (DAC) is not operational.
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This method should be called during initialization or when a reset is required
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to reinitialize the device and ensure proper operation.
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"""
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self.ctrl_reg |= AD9834_RESET
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self.write(self.ctrl_reg)
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@kernel
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def output_enable(self):
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"""
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Disable the DDS reset and start signal generation.
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This method clears :const:`AD9834_RESET`, allowing the AD9834 to begin generating
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signals. Once this method is called, the device will resume normal operation and
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output the generated waveform.
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This method should be called after configuration of the frequency and phase
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settings to activate the output.
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"""
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self.ctrl_reg &= ~AD9834_RESET
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self.write(self.ctrl_reg)
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@kernel
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def sleep(self, dac_pd: bool = False, clk_dis: bool = False):
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"""
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Put the AD9834 into sleep mode by selectively powering down the DAC and/or disabling
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the internal clock.
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This method controls the sleep mode behavior of the AD9834 by setting or clearing the
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corresponding bits in the control register. Two independent options can be specified:
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:param dac_pd: Set to ``True`` to power down the DAC (:const:`AD9834_SLEEP12` is set).
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``False`` will leave the DAC active.
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:param clk_dis: Set to ``True`` to disable the internal clock (:const:`AD9834_SLEEP1` is set).
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``False`` will keep the clock running.
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Both options can be enabled independently, allowing the DAC and/or clock to be powered down as needed.
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The method updates the control register and writes the changes to the AD9834 device.
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"""
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if dac_pd:
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self.ctrl_reg |= AD9834_SLEEP12
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else:
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self.ctrl_reg &= ~AD9834_SLEEP12
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if clk_dis:
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self.ctrl_reg |= AD9834_SLEEP1
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else:
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self.ctrl_reg &= ~AD9834_SLEEP1
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self.write(self.ctrl_reg)
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@kernel
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def awake(self):
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"""
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Exit sleep mode and restore normal operation.
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This method brings the AD9834 out of sleep mode by clearing any DAC power-down or
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internal clock disable settings. It calls :meth:`sleep()` with no arguments,
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effectively setting both ``dac_powerdown`` and ``internal_clk_disable`` to ``False``.
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The device will resume generating output based on the current frequency and phase
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settings.
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"""
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self.sleep()
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@kernel
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def config_sign_bit_out(
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self,
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high_z: bool = False,
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msb_2: bool = False,
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msb: bool = False,
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comp_out: bool = False,
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):
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"""
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Configure the ``SIGN BIT OUT`` pin for various output modes.
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This method sets the output mode for the ``SIGN BIT OUT`` pin of the AD9834 based on the provided flags.
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The user can enable one of several modes, including high impedance, MSB/2 output, MSB output,
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or comparator output. These modes are mutually exclusive, and passing ``True`` to one flag will
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configure the corresponding mode, while other flags should be left as ``False``.
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:param high_z: Set to ``True`` to place the ``SIGN BIT OUT`` pin in high impedance (disabled) mode.
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:param msb_2: Set to ``True`` to output DAC Data MSB divided by 2 on the ``SIGN BIT OUT`` pin.
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:param msb: Set to ``True`` to output DAC Data MSB on the ``SIGN BIT OUT`` pin.
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:param comp_out: Set to ``True`` to output the comparator signal on the ``SIGN BIT OUT`` pin.
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Only one flag should be set to ``True`` at a time. If no valid mode is selected, the ``SIGN BIT OUT``
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pin will default to high impedance mode.
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The method updates the control register with the appropriate configuration and writes it to the AD9834.
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"""
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if high_z:
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self.ctrl_reg &= ~AD9834_OPBITEN
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elif msb_2:
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self.ctrl_reg |= AD9834_OPBITEN
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self.ctrl_reg &= ~AD9834_MODE
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self.ctrl_reg &= ~AD9834_SIGN_PIB
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self.ctrl_reg &= ~AD9834_DIV2
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elif msb:
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self.ctrl_reg |= AD9834_OPBITEN
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self.ctrl_reg &= ~AD9834_MODE
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self.ctrl_reg &= ~AD9834_SIGN_PIB
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self.ctrl_reg |= AD9834_DIV2
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elif comp_out:
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self.ctrl_reg |= AD9834_OPBITEN
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self.ctrl_reg &= ~AD9834_MODE
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self.ctrl_reg |= AD9834_SIGN_PIB
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self.ctrl_reg |= AD9834_DIV2
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else:
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self.ctrl_reg &= ~AD9834_OPBITEN
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self.write(self.ctrl_reg)
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@kernel
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def enable_triangular_waveform(self):
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"""
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Enable triangular waveform generation.
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This method configures the AD9834 to output a triangular waveform. It does so
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by clearing :const:`AD9834_OPBITEN` in the control register and setting :const:`AD9834_MODE`.
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Once this method is called, the AD9834 will begin generating a triangular waveform
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at the frequency set for the selected frequency register.
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This method should be called when a triangular waveform is desired for signal
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generation. Ensure that the frequency is set appropriately before invoking this method.
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"""
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self.ctrl_reg &= ~AD9834_OPBITEN
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self.ctrl_reg |= AD9834_MODE
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self.write(self.ctrl_reg)
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@kernel
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def disable_triangular_waveform(self):
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"""
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Disable triangular waveform generation.
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This method disables the triangular waveform output by clearing :const:`AD9834_MODE`.
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After invoking this method, the AD9834 will cease generating a triangular waveform.
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The device can then be configured to output other waveform types if needed.
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This method should be called when switching to a different waveform type or
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when the triangular waveform is no longer required.
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"""
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self.ctrl_reg &= ~AD9834_MODE
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self.write(self.ctrl_reg)
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@kernel
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def write(self, data: TInt32):
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"""
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Write a 16-bit word to the AD9834.
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This method sends a 16-bit data word to the AD9834 via the SPI bus. The input
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data is left-shifted by 16 bits to ensure proper alignment for the SPI controller,
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allowing for accurate processing of the command by the AD9834.
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This method is used internally by other methods to update the control registers
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and frequency settings of the AD9834. It should not be called directly unless
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low-level register manipulation is required.
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:param data: The 16-bit word to be sent to the AD9834.
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"""
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self.bus.write(data << 16)
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321
artiq/test/coredevice/test_ad9834.py
Normal file
321
artiq/test/coredevice/test_ad9834.py
Normal file
@ -0,0 +1,321 @@
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from artiq.coredevice.ad9834 import (
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AD9834_B28,
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AD9834_DIV2,
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AD9834_FSEL,
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AD9834_HLB,
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AD9834_MODE,
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AD9834_OPBITEN,
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AD9834_PIN_SW,
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AD9834_PSEL,
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AD9834_RESET,
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AD9834_SIGN_PIB,
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AD9834_SLEEP1,
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AD9834_SLEEP12,
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FREQ_REGS,
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PHASE_REGS,
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)
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from artiq.experiment import *
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from artiq.language.units import MHz
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from artiq.test.hardware_testbench import ExperimentCase
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class AD9834Exp(EnvExperiment):
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def build(self, runner):
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self.setattr_device("core")
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self.dev = self.get_device("dds0")
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self.runner = runner
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def run(self):
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getattr(self, self.runner)()
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@kernel
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||||
def instantiate(self):
|
||||
pass
|
||||
|
||||
@kernel
|
||||
def init(self):
|
||||
self.core.break_realtime()
|
||||
self.dev.init()
|
||||
self.set_dataset("spi_freq", self.dev.spi_freq)
|
||||
self.set_dataset("clk_freq", self.dev.clk_freq)
|
||||
self.set_dataset("ctrl_reg", self.dev.ctrl_reg)
|
||||
|
||||
@kernel
|
||||
def set_frequency_reg_fail1(self):
|
||||
self.core.break_realtime()
|
||||
frequency = 10 * MHz
|
||||
self.dev.set_frequency_reg(19, frequency)
|
||||
|
||||
@kernel
|
||||
def set_frequency_reg_fail2(self):
|
||||
self.core.break_realtime()
|
||||
self.dev.set_frequency_reg(FREQ_REGS[0], 37.6 * MHz)
|
||||
|
||||
@kernel
|
||||
def set_frequency_reg(self):
|
||||
self.core.break_realtime()
|
||||
self.dev.init()
|
||||
self.dev.set_frequency_reg(FREQ_REGS[1], 19 * MHz)
|
||||
self.set_dataset("ctrl_reg", self.dev.ctrl_reg)
|
||||
|
||||
@kernel
|
||||
def set_frequency_reg_msb(self):
|
||||
self.core.break_realtime()
|
||||
self.dev.init()
|
||||
self.dev.ctrl_reg |= AD9834_B28
|
||||
self.dev.set_frequency_reg_msb(FREQ_REGS[0], 0x1111)
|
||||
self.set_dataset("ctrl_reg", self.dev.ctrl_reg)
|
||||
|
||||
@kernel
|
||||
def set_frequency_reg_lsb(self):
|
||||
self.core.break_realtime()
|
||||
self.dev.init()
|
||||
self.dev.ctrl_reg |= AD9834_B28 | AD9834_HLB
|
||||
self.dev.set_frequency_reg_lsb(FREQ_REGS[1], 0xFFFF)
|
||||
self.set_dataset("ctrl_reg", self.dev.ctrl_reg)
|
||||
|
||||
@kernel
|
||||
def select_frequency_reg_0(self):
|
||||
self.core.break_realtime()
|
||||
self.dev.ctrl_reg |= AD9834_FSEL | AD9834_PIN_SW
|
||||
self.dev.select_frequency_reg(FREQ_REGS[0])
|
||||
self.set_dataset("ctrl_reg", self.dev.ctrl_reg)
|
||||
|
||||
@kernel
|
||||
def select_frequency_reg_1(self):
|
||||
self.core.break_realtime()
|
||||
self.dev.ctrl_reg |= AD9834_PIN_SW
|
||||
self.dev.select_frequency_reg(FREQ_REGS[1])
|
||||
self.set_dataset("ctrl_reg", self.dev.ctrl_reg)
|
||||
|
||||
@kernel
|
||||
def set_phase_reg_fail(self):
|
||||
self.core.break_realtime()
|
||||
self.dev.set_phase_reg(19, 0x123)
|
||||
|
||||
@kernel
|
||||
def set_phase_reg(self):
|
||||
self.core.break_realtime()
|
||||
self.dev.init()
|
||||
self.dev.set_phase_reg(PHASE_REGS[0], 0x123)
|
||||
self.set_dataset("ctrl_reg", self.dev.ctrl_reg)
|
||||
|
||||
@kernel
|
||||
def select_phase_reg_0(self):
|
||||
self.core.break_realtime()
|
||||
self.dev.ctrl_reg |= AD9834_PSEL | AD9834_PIN_SW
|
||||
self.dev.select_phase_reg(PHASE_REGS[0])
|
||||
self.set_dataset("ctrl_reg", self.dev.ctrl_reg)
|
||||
|
||||
@kernel
|
||||
def select_phase_reg_1(self):
|
||||
self.core.break_realtime()
|
||||
self.dev.ctrl_reg |= AD9834_PIN_SW
|
||||
self.dev.select_phase_reg(PHASE_REGS[1])
|
||||
self.set_dataset("ctrl_reg", self.dev.ctrl_reg)
|
||||
|
||||
@kernel
|
||||
def enable_reset(self):
|
||||
self.core.break_realtime()
|
||||
self.dev.enable_reset()
|
||||
self.set_dataset("ctrl_reg", self.dev.ctrl_reg)
|
||||
|
||||
@kernel
|
||||
def output_enable(self):
|
||||
self.core.break_realtime()
|
||||
self.dev.ctrl_reg |= AD9834_RESET
|
||||
self.dev.output_enable()
|
||||
self.set_dataset("ctrl_reg", self.dev.ctrl_reg)
|
||||
|
||||
@kernel
|
||||
def sleep_dac_powerdown(self):
|
||||
self.core.break_realtime()
|
||||
self.dev.sleep(dac_pd=True)
|
||||
self.set_dataset("ctrl_reg", self.dev.ctrl_reg)
|
||||
|
||||
@kernel
|
||||
def sleep_internal_clk_disable(self):
|
||||
self.core.break_realtime()
|
||||
self.dev.sleep(clk_dis=True)
|
||||
self.set_dataset("ctrl_reg", self.dev.ctrl_reg)
|
||||
|
||||
@kernel
|
||||
def sleep(self):
|
||||
self.core.break_realtime()
|
||||
self.dev.sleep(dac_pd=True, clk_dis=True)
|
||||
self.set_dataset("ctrl_reg", self.dev.ctrl_reg)
|
||||
|
||||
@kernel
|
||||
def awake(self):
|
||||
self.core.break_realtime()
|
||||
self.dev.ctrl_reg |= AD9834_SLEEP1 | AD9834_SLEEP12
|
||||
self.dev.sleep()
|
||||
self.set_dataset("ctrl_reg", self.dev.ctrl_reg)
|
||||
|
||||
@kernel
|
||||
def sign_bit_high_z(self):
|
||||
self.core.break_realtime()
|
||||
self.dev.ctrl_reg |= AD9834_OPBITEN
|
||||
self.dev.config_sign_bit_out()
|
||||
self.set_dataset("ctrl_reg", self.dev.ctrl_reg)
|
||||
|
||||
@kernel
|
||||
def sign_bit_msb_2(self):
|
||||
self.core.break_realtime()
|
||||
self.dev.ctrl_reg |= AD9834_MODE | AD9834_SIGN_PIB | AD9834_DIV2
|
||||
self.dev.config_sign_bit_out(msb_2=True)
|
||||
self.set_dataset("ctrl_reg", self.dev.ctrl_reg)
|
||||
|
||||
@kernel
|
||||
def sign_bit_msb(self):
|
||||
self.core.break_realtime()
|
||||
self.dev.ctrl_reg |= AD9834_MODE | AD9834_SIGN_PIB
|
||||
self.dev.config_sign_bit_out(msb=True)
|
||||
self.set_dataset("ctrl_reg", self.dev.ctrl_reg)
|
||||
|
||||
@kernel
|
||||
def sign_bit_comp_out(self):
|
||||
self.core.break_realtime()
|
||||
self.dev.ctrl_reg |= AD9834_MODE
|
||||
self.dev.config_sign_bit_out(comp_out=True)
|
||||
self.set_dataset("ctrl_reg", self.dev.ctrl_reg)
|
||||
|
||||
@kernel
|
||||
def enable_triangular_waveform(self):
|
||||
self.core.break_realtime()
|
||||
self.dev.ctrl_reg |= AD9834_OPBITEN
|
||||
self.dev.enable_triangular_waveform()
|
||||
self.set_dataset("ctrl_reg", self.dev.ctrl_reg)
|
||||
|
||||
@kernel
|
||||
def disable_triangular_waveform(self):
|
||||
self.core.break_realtime()
|
||||
self.dev.ctrl_reg |= AD9834_MODE
|
||||
self.dev.disable_triangular_waveform()
|
||||
self.set_dataset("ctrl_reg", self.dev.ctrl_reg)
|
||||
|
||||
|
||||
class AD9834Test(ExperimentCase):
|
||||
def test_instantiate(self):
|
||||
self.execute(AD9834Exp, "instantiate")
|
||||
|
||||
def test_init(self):
|
||||
self.execute(AD9834Exp, "init")
|
||||
spi_freq = self.dataset_mgr.get("spi_freq")
|
||||
clk_freq = self.dataset_mgr.get("clk_freq")
|
||||
ctrl_reg = self.dataset_mgr.get("ctrl_reg")
|
||||
self.assertEqual(spi_freq, 10 * MHz)
|
||||
self.assertEqual(clk_freq, 75 * MHz)
|
||||
self.assertEqual(ctrl_reg, 0x0000 | AD9834_RESET)
|
||||
|
||||
def test_set_frequency_reg_fail(self):
|
||||
with self.assertRaises(ValueError):
|
||||
self.execute(AD9834Exp, "set_frequency_reg_fail1")
|
||||
with self.assertRaises(AssertionError):
|
||||
self.execute(AD9834Exp, "set_frequency_reg_fail2")
|
||||
|
||||
def test_set_frequency_reg(self):
|
||||
self.execute(AD9834Exp, "set_frequency_reg")
|
||||
ctrl_reg = self.dataset_mgr.get("ctrl_reg")
|
||||
self.assertEqual(ctrl_reg, 0x0000 | AD9834_RESET | AD9834_B28)
|
||||
|
||||
def test_set_frequency_reg_msb(self):
|
||||
self.execute(AD9834Exp, "set_frequency_reg_msb")
|
||||
ctrl_reg = self.dataset_mgr.get("ctrl_reg")
|
||||
self.assertEqual(ctrl_reg, 0x0000 | AD9834_RESET | AD9834_HLB)
|
||||
|
||||
def test_set_frequency_reg_lsb(self):
|
||||
self.execute(AD9834Exp, "set_frequency_reg_lsb")
|
||||
ctrl_reg = self.dataset_mgr.get("ctrl_reg")
|
||||
self.assertEqual(ctrl_reg, 0x0000 | AD9834_RESET)
|
||||
|
||||
def test_select_frequency_reg_0(self):
|
||||
self.execute(AD9834Exp, "select_frequency_reg_0")
|
||||
ctrl_reg = self.dataset_mgr.get("ctrl_reg")
|
||||
self.assertEqual(ctrl_reg, 0x0000)
|
||||
|
||||
def test_select_frequency_reg_1(self):
|
||||
self.execute(AD9834Exp, "select_frequency_reg_1")
|
||||
ctrl_reg = self.dataset_mgr.get("ctrl_reg")
|
||||
self.assertEqual(ctrl_reg, 0x0000 | AD9834_FSEL)
|
||||
|
||||
def test_set_phase_reg_fail(self):
|
||||
with self.assertRaises(ValueError):
|
||||
self.execute(AD9834Exp, "set_phase_reg_fail")
|
||||
|
||||
def test_set_phase_reg(self):
|
||||
self.execute(AD9834Exp, "set_phase_reg")
|
||||
ctrl_reg = self.dataset_mgr.get("ctrl_reg")
|
||||
self.assertEqual(ctrl_reg, 0x0000 | AD9834_RESET)
|
||||
|
||||
def test_select_phase_reg_0(self):
|
||||
self.execute(AD9834Exp, "select_phase_reg_0")
|
||||
ctrl_reg = self.dataset_mgr.get("ctrl_reg")
|
||||
self.assertEqual(ctrl_reg, 0x0000)
|
||||
|
||||
def test_select_phase_reg_1(self):
|
||||
self.execute(AD9834Exp, "select_phase_reg_1")
|
||||
ctrl_reg = self.dataset_mgr.get("ctrl_reg")
|
||||
self.assertEqual(ctrl_reg, 0x0000 | AD9834_PSEL)
|
||||
|
||||
def test_enable_reset(self):
|
||||
self.execute(AD9834Exp, "enable_reset")
|
||||
ctrl_reg = self.dataset_mgr.get("ctrl_reg")
|
||||
self.assertEqual(ctrl_reg, 0x0000 | AD9834_RESET)
|
||||
|
||||
def test_output_enable(self):
|
||||
self.execute(AD9834Exp, "output_enable")
|
||||
ctrl_reg = self.dataset_mgr.get("ctrl_reg")
|
||||
self.assertEqual(ctrl_reg, 0x0000)
|
||||
|
||||
def test_sleep_dac_powerdown(self):
|
||||
self.execute(AD9834Exp, "sleep_dac_powerdown")
|
||||
ctrl_reg = self.dataset_mgr.get("ctrl_reg")
|
||||
self.assertEqual(ctrl_reg, 0x0000 | AD9834_SLEEP12)
|
||||
|
||||
def test_sleep_internal_clk_disable(self):
|
||||
self.execute(AD9834Exp, "sleep_internal_clk_disable")
|
||||
ctrl_reg = self.dataset_mgr.get("ctrl_reg")
|
||||
self.assertEqual(ctrl_reg, 0x0000 | AD9834_SLEEP1)
|
||||
|
||||
def test_sleep(self):
|
||||
self.execute(AD9834Exp, "sleep")
|
||||
ctrl_reg = self.dataset_mgr.get("ctrl_reg")
|
||||
self.assertEqual(ctrl_reg, 0x0000 | AD9834_SLEEP1 | AD9834_SLEEP12)
|
||||
|
||||
def test_awake(self):
|
||||
self.execute(AD9834Exp, "awake")
|
||||
ctrl_reg = self.dataset_mgr.get("ctrl_reg")
|
||||
self.assertEqual(ctrl_reg, 0x0000)
|
||||
|
||||
def test_sign_bit_high_z(self):
|
||||
self.execute(AD9834Exp, "sign_bit_high_z")
|
||||
ctrl_reg = self.dataset_mgr.get("ctrl_reg")
|
||||
self.assertEqual(ctrl_reg, 0x0000)
|
||||
|
||||
def test_sign_bit_msb_2(self):
|
||||
self.execute(AD9834Exp, "sign_bit_msb_2")
|
||||
ctrl_reg = self.dataset_mgr.get("ctrl_reg")
|
||||
self.assertEqual(ctrl_reg, 0x0000 | AD9834_OPBITEN)
|
||||
|
||||
def test_sign_bit_msb(self):
|
||||
self.execute(AD9834Exp, "sign_bit_msb")
|
||||
ctrl_reg = self.dataset_mgr.get("ctrl_reg")
|
||||
self.assertEqual(ctrl_reg, 0x0000 | AD9834_OPBITEN | AD9834_DIV2)
|
||||
|
||||
def test_sign_bit_comp_out(self):
|
||||
self.execute(AD9834Exp, "sign_bit_comp_out")
|
||||
ctrl_reg = self.dataset_mgr.get("ctrl_reg")
|
||||
self.assertEqual(
|
||||
ctrl_reg, 0x0000 | AD9834_OPBITEN | AD9834_SIGN_PIB | AD9834_DIV2
|
||||
)
|
||||
|
||||
def test_enble_triangular_waveform(self):
|
||||
self.execute(AD9834Exp, "enable_triangular_waveform")
|
||||
ctrl_reg = self.dataset_mgr.get("ctrl_reg")
|
||||
self.assertEqual(ctrl_reg, 0x0000 | AD9834_MODE)
|
||||
|
||||
def test_disble_triangular_waveform(self):
|
||||
self.execute(AD9834Exp, "disable_triangular_waveform")
|
||||
ctrl_reg = self.dataset_mgr.get("ctrl_reg")
|
||||
self.assertEqual(ctrl_reg, 0x0000)
|
||||
@ -156,15 +156,39 @@ Common KC705 problems
|
||||
* When connected, the CLOCK adapter breaks the JTAG chain due to TDI not being connected to TDO on the FMC mezzanine.
|
||||
* On some boards, the JTAG USB connector is not correctly soldered.
|
||||
|
||||
VADJ
|
||||
""""
|
||||
|
||||
With the NIST CLOCK and QC2 adapters, for safe operation of the DDS buses (to prevent damage to the IO banks of the FPGA), the FMC VADJ rail of the KC705 should be changed to 3.3V. Plug the Texas Instruments USB-TO-GPIO PMBus adapter into the PMBus connector in the corner of the KC705 and use the Fusion Digital Power Designer software to configure (requires Windows). Write to chip number U55 (address 52), channel 4, which is the VADJ rail, to make it 3.3V instead of 2.5V. Power cycle the KC705 board to check that the startup voltage on the VADJ rail is now 3.3V.
|
||||
|
||||
EBAZ4205
|
||||
^^^^^^^^
|
||||
|
||||
The `EBAZ4205 <https://github.com/xjtuecho/EBAZ4205>`_ Zynq-SoC control card, originally used in the Ebit E9+ BTC miner, is a low-cost development board (around $20-$30 USD), making it an ideal option for experimenting with ARTIQ. To use the EBAZ4205, it's important to carefully follow the board documentation to configure it to boot from the SD card, as network booting via ``artiq_netboot`` is currently unsupported. This is because the Ethernet PHY is routed through the EMIO, requiring the FPGA to be programmed before the board can establish a network connection.
|
||||
|
||||
VADJ
|
||||
""""
|
||||
One useful application of the EBAZ4205 is controlling external devices like the AD9834 DDS Module from ZonRi Technology Co., Ltd. To establish communication between the EBAZ4205 and the AD9834 module, proper configuration of the SPI interface pins is essential. The board's flexibility allows for straightforward control of the DDS once the correct pinout is known. The table below details the necessary connections between the EBAZ4205 and the AD9834 module, including power, ground, and SPI signals.
|
||||
|
||||
With the NIST CLOCK and QC2 adapters, for safe operation of the DDS buses (to prevent damage to the IO banks of the FPGA), the FMC VADJ rail of the KC705 should be changed to 3.3V. Plug the Texas Instruments USB-TO-GPIO PMBus adapter into the PMBus connector in the corner of the KC705 and use the Fusion Digital Power Designer software to configure (requires Windows). Write to chip number U55 (address 52), channel 4, which is the VADJ rail, to make it 3.3V instead of 2.5V. Power cycle the KC705 board to check that the startup voltage on the VADJ rail is now 3.3V.
|
||||
+--------------------------+---------------------+----------------------------+
|
||||
| Pin on AD9834 Module | Chip Function | Connection on EBAZ4205 |
|
||||
+==========================+=====================+============================+
|
||||
| SCLK | SCLK | CLK: DATA3-19 (Pin V20) |
|
||||
+--------------------------+---------------------+----------------------------+
|
||||
| DATA | SDATA | MOSI: DATA3-17 (Pin U20) |
|
||||
+--------------------------+---------------------+----------------------------+
|
||||
| SYNC | FSYNC | CS_N: DATA3-15 (Pin P19) |
|
||||
+--------------------------+---------------------+----------------------------+
|
||||
| FSE (Tied to GND) | FSELECT | N/A: Bit Controlled |
|
||||
+--------------------------+---------------------+----------------------------+
|
||||
| PSE (Tied to GND) | PSELECT | N/A: Bit Controlled |
|
||||
+--------------------------+---------------------+----------------------------+
|
||||
| GND | Ground | GND: J8-1, J8-3 |
|
||||
+--------------------------+---------------------+----------------------------+
|
||||
| VIN | AVDD/DVDD | 3.3V: J8-2 |
|
||||
+--------------------------+---------------------+----------------------------+
|
||||
| RESET (Unused) | RESET | N/A: Bit Controlled |
|
||||
+--------------------------+---------------------+----------------------------+
|
||||
|
||||
For a step-by-step guide, see the `EBAZ4205 and AD9834 setup guide <https://newell.github.io/projects/ebaz4205>`_.
|
||||
|
||||
Variant details
|
||||
---------------
|
||||
|
||||
@ -85,6 +85,12 @@ RF generation drivers
|
||||
.. automodule:: artiq.coredevice.ad9914
|
||||
:members:
|
||||
|
||||
:mod:`artiq.coredevice.ad9834` module
|
||||
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
|
||||
|
||||
.. automodule:: artiq.coredevice.ad9834
|
||||
:members:
|
||||
|
||||
:mod:`artiq.coredevice.mirny` module
|
||||
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
|
||||
|
||||
|
||||
Loading…
Reference in New Issue
Block a user