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6234 Commits

Author SHA1 Message Date
Chris Ballance 6fc8439399 tweak moninj to allow old dashboard with new firmware 2018-08-02 19:34:14 +08:00
Chris Ballance 04cbc3237b test_moninj: test injection monitoring 2018-08-02 19:34:14 +08:00
Chris Ballance 47740c8930 share moninj injection state between dashboards 
Previously if one dashboard overrode a channel this was not visible on
any other dashboard - the channel appeared to operate normally.
 2018-08-02 19:34:14 +08:00
Robert Jördens 7d6a1b528d ad9912: add ftw_to_frequency 2018-08-02 11:19:12 +00:00
Robert Jördens e518a1f1d0 ad53xx: also increase slack after control readback 2018-08-02 11:19:12 +00:00
whitequark 5871d13da8 firmware: actually compact in config::compact(). 
Fixes #1116.
 2018-08-01 16:27:48 +00:00
David Nadlinger 829fca6112 pyon: Correctly deserialize bare NaNs 
This also fixes (non-numpy) lists containing NaNs.

Previously, accidentally storing a NaN in a dataset would
bring down large parts of the system.
 2018-07-30 11:08:56 +01:00
David Nadlinger 08ee91beb2 ad9910: Clarify chip_select range [nfc] 
`assert 3 <= chip_select <= 7` is rather opaque without looking
at the CPLD source code otherwise.
 2018-07-30 11:08:17 +01:00
David Nadlinger 6b89106578 ad53xx: Avoid sporadic RTIOUnderflow in init() 
I observed sporadic RTIO underflows on Kasli before, by ~2.5 µs,
so 5 µs extra slack should be plenty. No underflows since.
 2018-07-28 23:45:48 +01:00
Sebastien Bourdeauducq c00eb181fc conda: bump jesd204b 2018-07-28 13:17:44 +08:00
Sebastien Bourdeauducq e4d48a78eb drtio: wait for remote to ack TSC synchronization 
Sayma takes a long time after TSC sync to align SYSREF, and this caused two issues:
1. Aux packets getting lost and causing error reports
2. DRTIO links reported up and kernels proceeding despite the DACs not being properly synced.
 2018-07-26 20:28:17 +08:00
Sebastien Bourdeauducq 83de8b2ba2 drtio: add ping timeout during link init 2018-07-26 20:27:53 +08:00
Sebastien Bourdeauducq 446f791180 firmware: simplify SYSREF DRTIO alignment 2018-07-26 19:37:59 +08:00
Sebastien Bourdeauducq f8c17528e7 satman: use new SYSREF code 2018-07-26 16:26:57 +08:00
Sebastien Bourdeauducq 32c95ac034 sayma: automated DAC SYSREF phase calibration 2018-07-26 16:23:55 +08:00
Sebastien Bourdeauducq dbcf2fe9b4 firmware: remove 'chip found' messages on Sayma 2018-07-26 16:07:37 +08:00
Sebastien Bourdeauducq d523d03f71 sayma: automated FPGA SYSREF phase offset calibration 2018-07-26 14:53:28 +08:00
Sebastien Bourdeauducq 0a9d3638ee config: add write_int 2018-07-26 14:49:32 +08:00
Sebastien Bourdeauducq 19c51c644e grabber: cleanup GRABBER_STATE 2018-07-24 19:08:51 +08:00
Sebastien Bourdeauducq fb96c1140e grabber: add coredevice driver 2018-07-24 18:06:44 +08:00
Sebastien Bourdeauducq b38c685857 grabber: fix pix.stb 2018-07-24 11:32:32 +08:00
Sebastien Bourdeauducq 60a7e0e40d grabber: use usual order of ROI coordinates in cfg addresses 2018-07-24 10:55:13 +08:00
Sebastien Bourdeauducq 015c592ab7 conda: bump jesd204b 2018-07-21 15:49:40 +08:00
Sebastien Bourdeauducq 7b75026391 grabber: add MultiReg to transfer ROI boundaries 2018-07-21 13:40:12 +08:00
Sebastien Bourdeauducq 4a4d0f8e51 grabber: fix missing variable rename 2018-07-21 13:39:46 +08:00
Sebastien Bourdeauducq 3638a966e1 kasli: add false path between RTIO and CL clocks 2018-07-21 13:26:13 +08:00
Sebastien Bourdeauducq 031de58d21 grabber: complete RTIO PHY, untested 2018-07-21 13:25:47 +08:00
Sebastien Bourdeauducq e3ba4b9516 grabber: minor ROI engine cleanup, export count_len, cap count width to 31 2018-07-21 13:25:13 +08:00
Sebastien Bourdeauducq 766d87f626 doc: artiq_coreconfig → artiq_coremgmt config. Closes #1111 2018-07-20 11:59:07 +08:00
Sebastien Bourdeauducq cab0ba408d fmcdio_vhdci_eem: cleanup and document 2018-07-20 09:57:03 +08:00
Sebastien Bourdeauducq d152506ecb sayma: update fmcdio_vhdci_eem demo 2018-07-19 15:47:20 +08:00
Sebastien Bourdeauducq 8dfcd463aa fmcdio_vhdci_eem: naming consistency 2018-07-19 15:46:04 +08:00
Sebastien Bourdeauducq fe93a454d6 fmcdio_vhdci_eem: fix direction shift register permutation and polarity 2018-07-19 15:16:21 +08:00
Sebastien Bourdeauducq e71cbe53a6 firmware: cleanup Cargo.lock 2018-07-18 10:37:43 +08:00
Sebastien Bourdeauducq 31f4f8792a sayma: add Urukul and Zotino to example device_db 2018-07-18 10:31:55 +08:00
Sebastien Bourdeauducq 25170a53e5 sayma: add back Urukul and Zotino 2018-07-18 10:27:54 +08:00
Sebastien Bourdeauducq 5e62910a8d examples: add Sayma VHDCI DIO 2018-07-17 23:28:05 +08:00
Sebastien Bourdeauducq 8b9a8be12a fmcdio_vhdci_eem: add dirctl word computation functions 2018-07-17 23:27:29 +08:00
Sebastien Bourdeauducq 82145b1263 examples: sayma_drtio → sayma_masterdac 2018-07-17 20:32:30 +08:00
Sebastien Bourdeauducq c7d96c2223 conda: bump migen 2018-07-17 20:30:23 +08:00
Sebastien Bourdeauducq 7fe76426fe fmcdio_vhdci_eem: commit missing part of previous commit 2018-07-17 20:30:13 +08:00
Sebastien Bourdeauducq d4d12e264d fmcdio_vhdci_eem: refactor 
This allows access to the pin allocation from kernels, which becomes useful
to configure the direction shift register.
 2018-07-17 20:13:59 +08:00
Sebastien Bourdeauducq 4fdc20bb11 sayma: disable Urukul and Zotino for now 
Ultrascale I/Os are being a pain as usual and the SPI core won't compile.
 2018-07-17 20:08:21 +08:00
Sebastien Bourdeauducq 8335085fd6 fmcdio_vhdci_eem: fix cc pins 2018-07-17 19:50:34 +08:00
Sebastien Bourdeauducq 8f7c0c1646 fmcdio_vhdci_eem: fix iostandard 2018-07-17 19:40:34 +08:00
Sebastien Bourdeauducq d724bd980c sayma: add EEMs to Master 2018-07-17 18:58:23 +08:00
Sebastien Bourdeauducq a0f2d8c2ea gateware: add FMCDIO/EEM adapter definitions 2018-07-17 18:58:16 +08:00
Sebastien Bourdeauducq 3645a6424e sayma: fix Master build 2018-07-17 18:56:33 +08:00
Sebastien Bourdeauducq 9b016dcd6d eem: support specifying I/O standard 
Xilinx FPGAs require different LVDS I/O standard names depending on I/O bank voltage.
 2018-07-17 18:55:17 +08:00
Sebastien Bourdeauducq 3168b193e6 kc705: remove Zotino and Urukul 
* use Kasli instead for using EEMs
* code required outdated VHDCI adapter 1.0
 2018-07-17 17:48:57 +08:00