Spaqin
8be945d5c7
Urukul monitoring ( #1142 , #1921 )
2022-07-07 10:52:53 +08:00
Spaqin
35f30ddf05
Expose TTLClockGen for Kasli JSONs ( #1886 )
2022-05-06 13:33:42 +08:00
Robert Jördens
591507a7c0
Merge pull request #1774 from m-labs/fastino-cic
...
Fastino cic
2021-10-28 17:44:20 +02:00
Robert Jördens
3f6bf33298
fastino: add interpolator support
2021-10-08 15:47:07 +00:00
Sebastien Bourdeauducq
cf9cf0ab6f
ttl_serdes_7series: add dci (HP bank) support
2021-02-07 22:32:18 +08:00
Sebastien Bourdeauducq
997a48fb31
ttl_serdes_ultrascale: fix, add dummy dci argument
2021-02-07 22:31:46 +08:00
Sebastien Bourdeauducq
bbe0c9162a
ttl_serdes_ultrascale: cleanup
2021-02-07 22:00:33 +08:00
Sebastien Bourdeauducq
3572e2a9c7
ttl_serdes_7series: fix
2021-02-07 21:41:13 +08:00
Sebastien Bourdeauducq
88c212b84f
ttl_serdes_7series: cleanup
2021-02-07 21:33:21 +08:00
Sebastien Bourdeauducq
db25f4e8f7
ttl_serdes_7series: use simpler I/O buffers
...
In theory equivalent with these parameters.
2021-02-07 20:10:37 +08:00
Sebastien Bourdeauducq
6bd9691ba8
gateware: remove TTL dead code
2021-02-07 19:58:02 +08:00
Robert Jördens
30d1acee9f
fastlink: fix fastino style link
2020-10-18 20:43:21 +00:00
Robert Jördens
868a9a1f0c
phaser: new multidds
2020-09-16 14:06:38 +00:00
Robert Jördens
c18f515bf9
phaser: rework rtio channels, sync_dly, init()
2020-09-16 12:23:07 +00:00
Robert Jördens
fdd2d6f2fb
phaser: SI methods
2020-09-12 11:02:37 +00:00
Robert Jördens
4e24700205
phaser: spelling
2020-09-09 16:52:52 +00:00
Robert Jördens
8aaeaa604e
phaser: share_lut
2020-09-07 16:06:35 +00:00
Robert Jördens
272dc5d36a
phaser: documentation
2020-08-28 16:36:44 +00:00
Robert Jördens
96fc248d7c
phaser: synchronize multidds to frame
2020-08-27 14:28:19 +00:00
Robert Jördens
c10ac2c92a
phaser: add trf, duc, interfaces, redo body assembly, use more natrual iq ordering (i lsb)
2020-08-27 14:26:09 +00:00
Robert Jördens
e5e2392240
phaser: wire up multidds
2020-08-26 17:12:41 +00:00
Robert Jördens
d1be1212ab
phaser: coredevice shim, dds [wip]
2020-08-26 15:10:50 +00:00
Robert Jördens
20fcfd95e9
phaser: coredevice shim, readback fix
2020-08-24 15:46:31 +00:00
Robert Jördens
bcefb06e19
phaser: ddb template, split crc
2020-08-24 14:51:50 +00:00
Robert Jördens
11c9def589
phaser: readback delay, test fastlink
2020-08-24 14:49:36 +00:00
Robert Jördens
63e4b95325
fastlink: rework crc injection
2020-08-23 19:41:13 +00:00
Robert Jördens
a27a03ab3c
fastlink: fix crc vs data width
2020-08-23 19:02:50 +00:00
Robert Jördens
7e584d0da1
fastino: use fastlink
2020-08-22 11:56:23 +00:00
Robert Jördens
3e99f1ce5a
phaser: refactor link
2020-08-22 11:56:23 +00:00
Robert Jördens
a34a647ec4
phaser: refactor fastlink
2020-08-22 11:56:23 +00:00
Robert Jördens
aa0154d8e2
phaser: initial
2020-08-22 11:56:23 +00:00
Robert Jördens
ea79ba4622
ttl_serdes: detect edges on short pulses
...
Edges on pulses shorter than the RTIO period were missed because the
reference sample and the last sample of the serdes word are the same.
This change enables detection of edges on pulses as short as the
serdes UI (and shorter as long as the pulse still hits a serdes sample
aperture).
In any RTIO period, only the leading event corresponding to the first
edge with slope according to sensitivity is registerd. If the channel is
sensitive to both rising and falling edges and if the pulse is contained
within an RTIO period, or if it is sensitive only to one edge slope and
there are multiple pulses in an RTIO period, only the leading event is
seen. Thus this possibility of lost events is still there. Only the
conditions under which loss occurs are reduced.
In testing with the kasli-ptb6 variant, this also improves resource
usage (a couple hundred LUT) and timing (0.1 ns WNS).
2020-04-13 13:21:03 +02:00
Robert Jördens
e803830b3b
fastino: support wide RTIO interface and channel groups
2020-03-05 17:55:04 +00:00
Robert Jördens
2c4e5bfee4
fastino: add [WIP]
2020-01-20 13:25:00 +01:00
Sebastien Bourdeauducq
6c948c7726
sayma: RF switch control is active-low on Basemod, invert
2020-01-16 08:59:52 +08:00
Sebastien Bourdeauducq
37d0a5dc19
rtio/ttl: expose OE
2019-10-16 18:48:20 +08:00
Sebastien Bourdeauducq
bc060b7f01
style
2019-10-16 18:18:11 +08:00
Robert Jördens
f0e87d2e59
grabber: remove unused code
2019-09-20 15:26:12 +02:00
David Nadlinger
0353966ef7
gateware/suservo: Sign-extend data on RTIO read-back
...
See GitHub #1327 for original patch by Brad Bondurant.
2019-06-14 23:46:16 +01:00
hartytp
cfe1f56f73
suservo: add some more comments to the RTServoMem to clarify the RTIO interface ( #1323 )
2019-05-17 16:12:35 +01:00
Sebastien Bourdeauducq
3e8fe3f29d
suservo: fix permissions
2019-02-08 14:54:02 +08:00
hartytp
87e85bcc14
suservo: fix coefficient data writing
...
Signed-off-by: Thomas Harty <thomas.harty@physics.ox.ac.uk>
2019-02-07 14:47:11 +01:00
David Nadlinger
a565f77538
Add gateware input event counter
2019-01-15 10:55:07 +00:00
Sebastien Bourdeauducq
0972d61e81
ttl_serdes_ultrascale: use GTH clock domains
2019-01-03 20:50:04 +08:00
Sebastien Bourdeauducq
4af8fd6a0d
ttl_serdes_ultrascale: fix Input
2019-01-03 20:14:54 +08:00
Sebastien Bourdeauducq
c56c0ba41f
rtio/dds: use write-only RT2WB
...
This saves one address bit and prevents issues with AD9914 and 8-bit addresses.
2018-11-26 07:38:15 +08:00
Sebastien Bourdeauducq
09141e5bee
rtio/wishbone: support write-only interface
2018-11-26 07:38:06 +08:00
Sebastien Bourdeauducq
450a035f9e
suservo: move overflowing RTIO address bits into data
2018-11-26 06:54:20 +08:00
Sebastien Bourdeauducq
60a7e0e40d
grabber: use usual order of ROI coordinates in cfg addresses
2018-07-24 10:55:13 +08:00
Sebastien Bourdeauducq
7b75026391
grabber: add MultiReg to transfer ROI boundaries
2018-07-21 13:40:12 +08:00