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01fa6c1c2e
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reorganize examples
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2018-02-19 15:46:08 +08:00 |
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4b4090518b
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drtio: clean up remnants of removed debug functions
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2018-02-19 15:14:32 +08:00 |
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c329c83676
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kasli: fix disable_si5324_ibuf no_retiming
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2018-02-19 12:19:05 +08:00 |
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a93decdef2
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kasli: disable DRTIO IBUFDS_GTE2 until Si5324 is initialized
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2018-02-19 00:48:37 +08:00 |
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94c20dfd4d
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drtio: fix misleading GenericRXSynchronizer comment
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2018-02-19 00:47:54 +08:00 |
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83abdd283a
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drtio: signal stable clock input to transceiver
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2018-02-18 22:29:30 +08:00 |
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c87636ed2b
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si5324: fix cfb21ca
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2018-02-18 11:38:20 +01:00 |
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caedcd5a15
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ad9912: cleanup, document init()
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2018-02-18 11:38:16 +01:00 |
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75c89422c9
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ad991[02]: sysclk can be 1 GHz
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2018-02-18 10:29:19 +00:00 |
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6ae1cc20aa
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conda: bump misoc (#908)
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2018-02-18 12:35:49 +08:00 |
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41adbef9a9
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conda: bump misoc
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2018-02-17 17:41:16 +08:00 |
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287d533437
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Revert "sayma_amc: remove RTM bitstream upload core. Closes #908"
This reverts commit 2d4a1340ea.
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2018-02-17 17:38:48 +08:00 |
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73985a9215
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sayma: remove constraints at outputs of serwb PLL (see misoc d1489ed)
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2018-02-17 17:38:17 +08:00 |
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039dee4c8e
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si5324: rename SI5324_FREE_RUNNING to SI5324_AS_SYNTHESIZER
The previous name was causing confusion with the FREE_RUN bit
that connects the crystal to CLKIN2.
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2018-02-17 13:54:50 +08:00 |
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cfb21ca126
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si5324: fix usage of external CLKIN2 reference
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2018-02-17 13:52:01 +08:00 |
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07a31f8d86
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conda: bump openocd
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2018-02-17 13:21:10 +08:00 |
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fb8b36cd41
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clean up ccc279b8
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2018-02-17 12:10:46 +08:00 |
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hartytp
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ccc279b8da
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rewrite HMC7043 init code without using ADI GUI outputs, working analog/digital delay
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2018-02-17 12:07:11 +08:00 |
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e41f49cc75
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kasli: opticlock 125 MHz, mark external reference case broken
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2018-02-16 17:23:15 +00:00 |
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e4db84e214
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doc: fix typo
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2018-02-17 00:11:48 +08:00 |
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7a5161d348
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conda: bump misoc (#902)
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2018-02-17 00:11:42 +08:00 |
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0ef33dd0d8
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manual: add note about the "correct" vivado version
close #910
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2018-02-15 14:21:17 +01:00 |
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7002bea0ab
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kasli: clean up urukul example more
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2018-02-15 14:21:17 +01:00 |
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4d42df2a7c
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kasli: set up Si5324 in standalone operation
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2018-02-15 20:32:58 +08:00 |
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c5ae81f452
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satman: remove unused 62.5MHz Si5324 settings
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2018-02-15 20:29:51 +08:00 |
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d7387611c0
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sayma: print RTM gateware version
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2018-02-15 19:31:58 +08:00 |
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whitequark
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d572c0c34d
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artiq_devtool: fix the hotswap action.
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2018-02-14 23:10:27 +00:00 |
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whitequark
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fe50018037
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firmware: make network tracing runtime switchable.
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2018-02-14 23:03:20 +00:00 |
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2adba3ed33
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urukul: document ad9912, and cpld, fix api
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2018-02-14 09:45:17 +01:00 |
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ede98679fc
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ad9910: add documentation
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2018-02-14 09:05:03 +01:00 |
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b6395a809b
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kasli: remove old urukul test code
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2018-02-13 22:16:57 +01:00 |
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be693bc8a9
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opticlock: examples
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2018-02-13 22:13:40 +01:00 |
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a3d136d30d
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opticlock: wire urukul and novogorny
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2018-02-13 22:13:40 +01:00 |
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7f1bfddeda
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ad9910: tweak spi timing for higher speed
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2018-02-13 22:13:40 +01:00 |
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6a6695924f
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urukul: proto 8
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2018-02-13 22:13:40 +01:00 |
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bc6af03a61
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urukul: (proto 7) drop att_le
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2018-02-13 22:13:40 +01:00 |
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df177bfd5b
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use new misoc identifier
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2018-02-13 20:38:48 +08:00 |
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ab5f397fea
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sed/fifos: use AsyncFIFOBuffered
(D)RTIO now passes timing at 150MHz on Kasli.
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2018-02-13 20:02:51 +08:00 |
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00f42f912b
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rename 'RTM identifier' to 'RTM magic number'
Avoids confusion with the MiSoC identifier (containing the ARTIQ version).
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2018-02-13 20:02:51 +08:00 |
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96b948f57f
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remote_csr: add sanity check of CSR CSV type column
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2018-02-13 20:02:51 +08:00 |
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e67a289e2b
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examples: add SAWG sines (DAC synchronization test)
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2018-02-13 20:02:51 +08:00 |
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Florent Kermarrec
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bfdda340fd
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drtio/transceiver/gtp_7series: use parameters from xilinx wizard
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2018-02-13 00:23:59 +01:00 |
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Florent Kermarrec
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180c28551d
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drtio/gateware/transceiver/gtp_7series: add power down state before reset on rx (seems to make restart reliable)
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2018-02-09 20:17:02 +01:00 |
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2d4a1340ea
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sayma_amc: remove RTM bitstream upload core. Closes #908
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2018-02-07 12:27:35 +08:00 |
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whitequark
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61c64a76be
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gateware: use a per-variant subfolder in --output-dir. (fixes #912)
This commit also adds support for --variant and --args
to artiq-devtool.
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2018-02-06 08:19:01 +00:00 |
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Florent Kermarrec
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e80b481032
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firmware/libboard_artiq/hmc830_7043.rs: add template for sys_ref phase configuration for dac1/dac2 and fpga
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2018-02-05 13:40:17 +01:00 |
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Florent Kermarrec
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e50bebb63d
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firmware/liboard_artiq/ad9154.rs: add checks for jesd subclass 1 (verify that we receive the sysref and that phase error is within the specified window error threshold).
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2018-02-05 13:39:30 +01:00 |
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4c22d64ee4
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conda: sync artiq/artiq-dev dependencies
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2018-01-30 08:36:55 +01:00 |
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9fca7b8faa
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artiq_flash: also report sayma AMC SYSMONE1 data
requires hardware patch (https://github.com/m-labs/sinara/issues/495)
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2018-01-30 15:17:11 +08:00 |
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fb8c779b4f
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artiq_flash: report XADC data
* bump openocd
* only kasli, kc705, sayma rtm so far
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2018-01-30 14:56:50 +08:00 |
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