|
|
91a4a7b0ee
|
kasli: free run si5324 on opticlock for now
|
2018-02-21 13:37:29 +00:00 |
|
|
|
7a1d71502a
|
ttl_serdes_7series: drive IBUF and INTERM disables from serdes
|
2018-02-21 13:37:29 +00:00 |
|
|
|
476e4fdd56
|
ttl_serdes_7series: disable IBUF and INTERM when output
|
2018-02-21 13:37:29 +00:00 |
|
Florent Kermarrec
|
afc16a67b6
|
firmware/liboard/sdram.rs: iterate read multiple times in read_delays to avoid false positives
|
2018-02-21 14:15:35 +01:00 |
|
whitequark
|
86ceee570f
|
compiler: reject calls with unexpected keyword arguments.
Fixes #924.
|
2018-02-21 11:37:12 +00:00 |
|
|
|
7986391422
|
manual: update Kasli section
|
2018-02-21 12:04:14 +08:00 |
|
|
|
6c4681e7d2
|
manual: fix minor errors
|
2018-02-21 11:57:57 +08:00 |
|
|
|
932fa884cc
|
conda: add recipes for Kasli DRTIO
|
2018-02-21 11:15:01 +08:00 |
|
|
|
eed64a6d6b
|
conda: fix openocd dependency
|
2018-02-21 10:35:31 +08:00 |
|
|
|
f060d6e1b3
|
drtio: increase A7 clock aligner check period
|
2018-02-20 18:50:35 +08:00 |
|
|
|
738654c783
|
drtio: support remote RTIO resets
|
2018-02-20 18:48:54 +08:00 |
|
|
|
f15b4bdde7
|
style
|
2018-02-20 18:47:59 +08:00 |
|
|
|
7d9c7ada71
|
drtio: fix test infinite loop
|
2018-02-20 17:42:00 +08:00 |
|
|
|
ad2c9590d0
|
drtio: rewrite/fix reset and link bringup/teardown
|
2018-02-20 17:26:43 +08:00 |
|
|
|
bfabf3c906
|
conda: bump migen (9c3a301)
|
2018-02-19 13:07:17 +00:00 |
|
|
|
7e02d8245c
|
kasli: false paths
* don't bother with the round trip OSERDESE2 -> ... -> pad -> ... ->
ISERDESE2
* clock groups with derived clocks c.f. migen 9c3a301
|
2018-02-19 13:05:11 +00:00 |
|
|
|
0f4549655b
|
sayma: use Xilinx RX synchronizer
Cannot be used on Kasli, this breaks the bitstream entirely (nothing on UART).
|
2018-02-19 17:49:53 +08:00 |
|
|
|
52049cf36a
|
drtio: add Xilinx RX synchronizer
|
2018-02-19 17:49:43 +08:00 |
|
|
|
3bc575bee7
|
drtio: add missing define for Sayma master
|
2018-02-19 17:11:21 +08:00 |
|
|
|
7376ab0ff8
|
drtio: fix Sayma after 83abdd28
|
2018-02-19 17:10:55 +08:00 |
|
Florent Kermarrec
|
f5831af535
|
drtio/transceiver/gtp_7series_init: don't reset gtp rx on power down
|
2018-02-19 10:03:19 +01:00 |
|
Florent Kermarrec
|
89a158c0c9
|
drtio/transceiver/gtp_7series_init: remove dead code
|
2018-02-19 10:02:23 +01:00 |
|
Florent Kermarrec
|
782051f474
|
drtio/transceiver/gtp_7series_init: add no retiming on gtp resets
|
2018-02-19 09:59:50 +01:00 |
|
|
|
01fa6c1c2e
|
reorganize examples
|
2018-02-19 15:46:08 +08:00 |
|
|
|
4b4090518b
|
drtio: clean up remnants of removed debug functions
|
2018-02-19 15:14:32 +08:00 |
|
|
|
c329c83676
|
kasli: fix disable_si5324_ibuf no_retiming
|
2018-02-19 12:19:05 +08:00 |
|
|
|
a93decdef2
|
kasli: disable DRTIO IBUFDS_GTE2 until Si5324 is initialized
|
2018-02-19 00:48:37 +08:00 |
|
|
|
94c20dfd4d
|
drtio: fix misleading GenericRXSynchronizer comment
|
2018-02-19 00:47:54 +08:00 |
|
|
|
83abdd283a
|
drtio: signal stable clock input to transceiver
|
2018-02-18 22:29:30 +08:00 |
|
|
|
c87636ed2b
|
si5324: fix cfb21ca
|
2018-02-18 11:38:20 +01:00 |
|
|
|
caedcd5a15
|
ad9912: cleanup, document init()
|
2018-02-18 11:38:16 +01:00 |
|
|
|
75c89422c9
|
ad991[02]: sysclk can be 1 GHz
|
2018-02-18 10:29:19 +00:00 |
|
|
|
6ae1cc20aa
|
conda: bump misoc (#908)
|
2018-02-18 12:35:49 +08:00 |
|
|
|
41adbef9a9
|
conda: bump misoc
|
2018-02-17 17:41:16 +08:00 |
|
|
|
287d533437
|
Revert "sayma_amc: remove RTM bitstream upload core. Closes #908"
This reverts commit 2d4a1340ea.
|
2018-02-17 17:38:48 +08:00 |
|
|
|
73985a9215
|
sayma: remove constraints at outputs of serwb PLL (see misoc d1489ed)
|
2018-02-17 17:38:17 +08:00 |
|
|
|
039dee4c8e
|
si5324: rename SI5324_FREE_RUNNING to SI5324_AS_SYNTHESIZER
The previous name was causing confusion with the FREE_RUN bit
that connects the crystal to CLKIN2.
|
2018-02-17 13:54:50 +08:00 |
|
|
|
cfb21ca126
|
si5324: fix usage of external CLKIN2 reference
|
2018-02-17 13:52:01 +08:00 |
|
|
|
07a31f8d86
|
conda: bump openocd
|
2018-02-17 13:21:10 +08:00 |
|
|
|
fb8b36cd41
|
clean up ccc279b8
|
2018-02-17 12:10:46 +08:00 |
|
hartytp
|
ccc279b8da
|
rewrite HMC7043 init code without using ADI GUI outputs, working analog/digital delay
|
2018-02-17 12:07:11 +08:00 |
|
|
|
e41f49cc75
|
kasli: opticlock 125 MHz, mark external reference case broken
|
2018-02-16 17:23:15 +00:00 |
|
|
|
e4db84e214
|
doc: fix typo
|
2018-02-17 00:11:48 +08:00 |
|
|
|
7a5161d348
|
conda: bump misoc (#902)
|
2018-02-17 00:11:42 +08:00 |
|
|
|
0ef33dd0d8
|
manual: add note about the "correct" vivado version
close #910
|
2018-02-15 14:21:17 +01:00 |
|
|
|
7002bea0ab
|
kasli: clean up urukul example more
|
2018-02-15 14:21:17 +01:00 |
|
|
|
4d42df2a7c
|
kasli: set up Si5324 in standalone operation
|
2018-02-15 20:32:58 +08:00 |
|
|
|
c5ae81f452
|
satman: remove unused 62.5MHz Si5324 settings
|
2018-02-15 20:29:51 +08:00 |
|
|
|
d7387611c0
|
sayma: print RTM gateware version
|
2018-02-15 19:31:58 +08:00 |
|
whitequark
|
d572c0c34d
|
artiq_devtool: fix the hotswap action.
|
2018-02-14 23:10:27 +00:00 |
|
