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Author SHA1 Message Date
occheung
158a7be74c ad9910: avoid unnecessary write/param 
Credit: Solution proposed by @pmldrmota in https://github.com/m-labs/artiq/pull/1584#issuecomment-987774353
 2021-12-08 11:22:02 +08:00
occheung
1064fdff2e ad9910/set_mu: comment on caveats when setting register 2021-12-07 14:30:22 +08:00
occheung
41b2c8d07a Merge branch 'master' into ad9910 2021-12-07 13:57:30 +08:00
Sébastien Bourdeauducq
311a818a49
Merge pull request #1544 from airwoodix/dataset-compression 
datasets: support compression in HDF5 archives
 2021-12-06 12:43:19 +08:00
Sébastien Bourdeauducq
1def0d98c5
Merge branch 'master' into dataset-compression 2021-12-06 12:40:30 +08:00
Leon Riesebos
7ffe4dc2e3 coredevice: set default pow for ad9912 set_mu() 2021-12-06 12:34:55 +08:00
Leon Riesebos
9e3ea4e8ef coredevice: fixed type annotations for AD9910 2021-12-06 12:34:55 +08:00
Sebastien Bourdeauducq
12512bfb2f flake: get rid of TARGET_AR 2021-12-05 14:37:09 +08:00
Steve Fan
4a6bea479a
Host report for async error upon kernel termination (#1791) 
Closes #1644
 2021-12-04 13:33:24 +08:00
Sebastien Bourdeauducq
9bbf7eb485 flake: use ed25519 key for hitl 2021-12-03 18:35:10 +08:00
mwojcik
f8a649deda release notes: mention 100mhz support 2021-12-03 17:19:11 +08:00
mwojcik
7953f3d705 kc705: add drtio 100mhz clk switch 2021-12-03 17:19:11 +08:00
mwojcik
f281112779 satman: add 100mhz si5324 settings 
siphaser: add calculated vco for 100mhz comment
 2021-12-03 17:19:11 +08:00
mwojcik
eec3ea6589 siphaser: add support for 100mhz rtio 2021-12-03 17:19:11 +08:00
Sebastien Bourdeauducq
163f5d9128 flake: debug hitl auth failures 2021-12-03 17:16:54 +08:00
Etienne Wodey
9f830b86c0
kasli: add SED lanes count option to HW description JSON file (#1745) 
Signed-off-by: Etienne Wodey <etienne.wodey@aqt.eu>
 2021-12-03 17:05:35 +08:00
Sebastien Bourdeauducq
b8e7add785 language: remove deprecated set_dataset(..., save=...) 2021-12-01 22:41:34 +08:00
Sebastien Bourdeauducq
5a923a0956 flake: switch to nixos- branch 2021-12-01 22:39:24 +08:00
David Nadlinger
c6039479e4 compiler: Add lit test for call site attributes [nfc] 2021-11-27 04:46:07 +00:00
David Nadlinger
63b5727a0c compiler: Also emit byval argument attributes at call sites 
See previous commit.

GitHub: Fixes #1599.
 2021-11-27 04:45:50 +00:00
David Nadlinger
9b01db3d11 compiler: Emit sret call site argument attributes 
LLVM 6 seemed not to mind the mismatch, but more recent
versions produce miscompilations without this.

Needs llvmlite support (GitHub: numba/llvmlite#702).
 2021-11-27 04:44:41 +00:00
Sebastien Bourdeauducq
6a433b2fce artiq_sinara_tester: test Urukul attenuator digital control 2021-11-24 18:57:16 +08:00
occheung
5ed9e49b94 changelog: update drtio protocol 2021-11-24 12:00:56 +08:00
occheung
9423428bb0 drtio: fix crc32 offset address 2021-11-24 12:00:56 +08:00
Sebastien Bourdeauducq
7307b30213 flake: update to nixpkgs 21.11 2021-11-23 12:15:17 +08:00
Harry Ho
b49f813b17 artiq_flash: ignore checking non-RTM artifacts if unused 2021-11-18 16:59:32 +08:00
Peter Drmota
20e079a381
AD9910 driver feature extension and SUServo IIR readability (#1500) 
* coredevice.ad9910: Add set_cfr2 function and extend arguments of set_cfr1 and set_sync

* SUServo: Wrap CPLD and DDS devices in a list

* SUServo: Refactor [nfc]

Co-authored-by: drmota <peter.drmota@physics.ox.ac.uk>
Co-authored-by: David Nadlinger <code@klickverbot.at>
 2021-11-15 12:09:16 +08:00
Peter Drmota
a050335ada coredevice: Change Urukul default single-tone profile to 7 
This allows using the internal profile control in RAM modulation mode (which always starts to play back at profile 0) without competing for the content of the profile 0 register used in single tone mode.

Signed-off-by: Peter Drmota <peter.drmota@physics.ox.ac.uk>
 2021-11-14 20:54:40 +01:00
Sebastien Bourdeauducq
f0c50c80e6 flake: update dependencies 2021-11-12 19:28:51 +08:00
Sebastien Bourdeauducq
46604300a2 flake: update dependencies 2021-11-10 14:59:02 +08:00
Sebastien Bourdeauducq
c029977a27 flake: update dependencies 2021-11-10 09:54:34 +08:00
Sebastien Bourdeauducq
80115fcc02 flake: apply llvmlite callsite patch 2021-11-08 17:34:30 +08:00
occheung
ac2f55b3ff flake: patch llvmlite 2021-11-08 16:59:08 +08:00
occheung
db3e5e83e6 bump misoc 2021-11-08 16:59:08 +08:00
occheung
09945ecc4d gateware: fix drtio/dma tests 2021-11-08 16:59:08 +08:00
occheung
02119282b8 build_soc: build VexRiscv_G if not kasli v1.x 2021-11-08 16:59:08 +08:00
occheung
750b0ce46d ddb_temp: select appropriate compiler target 2021-11-08 16:59:08 +08:00
occheung
531670d6c5 dyld: check ABI 2021-11-08 16:59:08 +08:00
occheung
0f660735bf ll_gen: adjust csr address by detecting target class 2021-11-08 16:59:08 +08:00
occheung
0755757601 compiler/tb: use FPU 2021-11-08 16:59:08 +08:00
occheung
0d708cd61a compiler/target: split RISCV target into float/non-float 2021-11-08 16:59:08 +08:00
occheung
03b803e764 firmware: adjust csr separation 2021-11-08 16:59:08 +08:00
occheung
b3e315e24a rust: find json file using CARGO_TRIPLE 2021-11-08 16:59:08 +08:00
occheung
0898e101e2 board_misoc: reuse riscv dir for comm & kernel 2021-11-08 16:59:08 +08:00
occheung
cb247f235f gateware: pass adr_w/data_w to submodules 2021-11-08 16:59:08 +08:00
occheung
90f944481c kernel_cpu: add fpu if not kasli v1.x 2021-11-08 16:59:08 +08:00
occheung
d84ad0095b comm_cpu: select 64b bus if not kasli v1.x 2021-11-08 16:59:08 +08:00
occheung
dd68b4ab82 mailbox: parametrize address width 2021-11-08 16:59:08 +08:00
occheung
c6e0e26440 drtio: accept 32b/64b bus 2021-11-08 16:59:08 +08:00
occheung
8da924ec0f dma: set conversion granularity using bus width 2021-11-08 16:59:08 +08:00