whitequark
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96f697ec96
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firmware: update compiler_builtins to unbreak __gtdf2.
Fixes #883.
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2018-02-21 15:21:48 +00:00 |
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a63fd306af
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urukul: use spi2
* switch kc705 and kasli targets to spi2 gateware on urukul
* rewrite urukul, ad9912, ad9910
* update example experiments, device_dbs
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2018-02-21 15:00:28 +00:00 |
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37a0d6580b
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spi2: add RTIO gateware and coredevice driver
1006218997
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2018-02-21 13:37:36 +00:00 |
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91a4a7b0ee
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kasli: free run si5324 on opticlock for now
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2018-02-21 13:37:29 +00:00 |
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7a1d71502a
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ttl_serdes_7series: drive IBUF and INTERM disables from serdes
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2018-02-21 13:37:29 +00:00 |
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476e4fdd56
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ttl_serdes_7series: disable IBUF and INTERM when output
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2018-02-21 13:37:29 +00:00 |
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Florent Kermarrec
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afc16a67b6
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firmware/liboard/sdram.rs: iterate read multiple times in read_delays to avoid false positives
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2018-02-21 14:15:35 +01:00 |
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whitequark
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86ceee570f
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compiler: reject calls with unexpected keyword arguments.
Fixes #924.
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2018-02-21 11:37:12 +00:00 |
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7986391422
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manual: update Kasli section
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2018-02-21 12:04:14 +08:00 |
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6c4681e7d2
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manual: fix minor errors
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2018-02-21 11:57:57 +08:00 |
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932fa884cc
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conda: add recipes for Kasli DRTIO
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2018-02-21 11:15:01 +08:00 |
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eed64a6d6b
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conda: fix openocd dependency
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2018-02-21 10:35:31 +08:00 |
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f060d6e1b3
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drtio: increase A7 clock aligner check period
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2018-02-20 18:50:35 +08:00 |
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738654c783
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drtio: support remote RTIO resets
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2018-02-20 18:48:54 +08:00 |
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f15b4bdde7
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style
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2018-02-20 18:47:59 +08:00 |
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7d9c7ada71
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drtio: fix test infinite loop
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2018-02-20 17:42:00 +08:00 |
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ad2c9590d0
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drtio: rewrite/fix reset and link bringup/teardown
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2018-02-20 17:26:43 +08:00 |
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bfabf3c906
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conda: bump migen (9c3a301)
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2018-02-19 13:07:17 +00:00 |
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7e02d8245c
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kasli: false paths
* don't bother with the round trip OSERDESE2 -> ... -> pad -> ... ->
ISERDESE2
* clock groups with derived clocks c.f. migen 9c3a301
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2018-02-19 13:05:11 +00:00 |
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0f4549655b
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sayma: use Xilinx RX synchronizer
Cannot be used on Kasli, this breaks the bitstream entirely (nothing on UART).
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2018-02-19 17:49:53 +08:00 |
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52049cf36a
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drtio: add Xilinx RX synchronizer
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2018-02-19 17:49:43 +08:00 |
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3bc575bee7
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drtio: add missing define for Sayma master
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2018-02-19 17:11:21 +08:00 |
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7376ab0ff8
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drtio: fix Sayma after 83abdd28
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2018-02-19 17:10:55 +08:00 |
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Florent Kermarrec
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f5831af535
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drtio/transceiver/gtp_7series_init: don't reset gtp rx on power down
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2018-02-19 10:03:19 +01:00 |
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Florent Kermarrec
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89a158c0c9
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drtio/transceiver/gtp_7series_init: remove dead code
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2018-02-19 10:02:23 +01:00 |
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Florent Kermarrec
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782051f474
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drtio/transceiver/gtp_7series_init: add no retiming on gtp resets
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2018-02-19 09:59:50 +01:00 |
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01fa6c1c2e
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reorganize examples
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2018-02-19 15:46:08 +08:00 |
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4b4090518b
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drtio: clean up remnants of removed debug functions
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2018-02-19 15:14:32 +08:00 |
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c329c83676
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kasli: fix disable_si5324_ibuf no_retiming
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2018-02-19 12:19:05 +08:00 |
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a93decdef2
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kasli: disable DRTIO IBUFDS_GTE2 until Si5324 is initialized
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2018-02-19 00:48:37 +08:00 |
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94c20dfd4d
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drtio: fix misleading GenericRXSynchronizer comment
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2018-02-19 00:47:54 +08:00 |
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83abdd283a
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drtio: signal stable clock input to transceiver
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2018-02-18 22:29:30 +08:00 |
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c87636ed2b
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si5324: fix cfb21ca
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2018-02-18 11:38:20 +01:00 |
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caedcd5a15
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ad9912: cleanup, document init()
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2018-02-18 11:38:16 +01:00 |
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75c89422c9
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ad991[02]: sysclk can be 1 GHz
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2018-02-18 10:29:19 +00:00 |
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6ae1cc20aa
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conda: bump misoc (#908)
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2018-02-18 12:35:49 +08:00 |
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41adbef9a9
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conda: bump misoc
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2018-02-17 17:41:16 +08:00 |
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287d533437
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Revert "sayma_amc: remove RTM bitstream upload core. Closes #908"
This reverts commit 2d4a1340ea.
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2018-02-17 17:38:48 +08:00 |
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73985a9215
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sayma: remove constraints at outputs of serwb PLL (see misoc d1489ed)
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2018-02-17 17:38:17 +08:00 |
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039dee4c8e
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si5324: rename SI5324_FREE_RUNNING to SI5324_AS_SYNTHESIZER
The previous name was causing confusion with the FREE_RUN bit
that connects the crystal to CLKIN2.
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2018-02-17 13:54:50 +08:00 |
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cfb21ca126
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si5324: fix usage of external CLKIN2 reference
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2018-02-17 13:52:01 +08:00 |
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07a31f8d86
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conda: bump openocd
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2018-02-17 13:21:10 +08:00 |
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fb8b36cd41
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clean up ccc279b8
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2018-02-17 12:10:46 +08:00 |
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hartytp
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ccc279b8da
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rewrite HMC7043 init code without using ADI GUI outputs, working analog/digital delay
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2018-02-17 12:07:11 +08:00 |
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e41f49cc75
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kasli: opticlock 125 MHz, mark external reference case broken
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2018-02-16 17:23:15 +00:00 |
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e4db84e214
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doc: fix typo
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2018-02-17 00:11:48 +08:00 |
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7a5161d348
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conda: bump misoc (#902)
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2018-02-17 00:11:42 +08:00 |
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0ef33dd0d8
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manual: add note about the "correct" vivado version
close #910
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2018-02-15 14:21:17 +01:00 |
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7002bea0ab
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kasli: clean up urukul example more
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2018-02-15 14:21:17 +01:00 |
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4d42df2a7c
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kasli: set up Si5324 in standalone operation
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2018-02-15 20:32:58 +08:00 |
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