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artiq
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Merge branch 'syncrtio'

pull/2051/head
Sebastien Bourdeauducq 2023-01-12 16:44:54 +08:00
parent babbbfadb3 70edc9c5c6
commit b8968262d7
4 changed files with 13 additions and 13 deletions
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2
artiq/gateware/drtio/core.py
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@ -77,7 +77,7 @@ class DRTIOSatellite(Module):
self.reset = CSRStorage(reset=1) self.reset = CSRStorage(reset=1)
self.reset_phy = CSRStorage(reset=1) self.reset_phy = CSRStorage(reset=1)
self.tsc_loaded = CSR() self.tsc_loaded = CSR()
# master interface in the rtio domain # master interface in the sys domain
self.cri = cri.Interface() self.cri = cri.Interface()
self.async_errors = Record(async_errors_layout) self.async_errors = Record(async_errors_layout)

6
artiq/gateware/targets/kc705.py
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@ -112,7 +112,7 @@ class _StandaloneBase(MiniSoC, AMPSoC):
cdr_clk_buf = Signal() cdr_clk_buf = Signal()
self.config["HAS_SI5324"] = None self.config["HAS_SI5324"] = None
self.submodules.si5324_rst_n = gpio.GPIOOut(self.platform.request("si5324_33").rst_n) self.submodules.si5324_rst_n = gpio.GPIOOut(self.platform.request("si5324_33").rst_n, reset_out=1)
self.csr_devices.append("si5324_rst_n") self.csr_devices.append("si5324_rst_n")
self.specials += [ self.specials += [
Instance("IBUFDS_GTE2", Instance("IBUFDS_GTE2",
@ -254,7 +254,7 @@ class _MasterBase(MiniSoC, AMPSoC):
self.add_memory_group("drtioaux_mem", drtioaux_memory_group) self.add_memory_group("drtioaux_mem", drtioaux_memory_group)
self.config["RTIO_FREQUENCY"] = str(self.drtio_transceiver.rtio_clk_freq/1e6) self.config["RTIO_FREQUENCY"] = str(self.drtio_transceiver.rtio_clk_freq/1e6)
self.submodules.si5324_rst_n = gpio.GPIOOut(platform.request("si5324_33").rst_n) self.submodules.si5324_rst_n = gpio.GPIOOut(platform.request("si5324_33").rst_n, reset_out=1)
self.csr_devices.append("si5324_rst_n") self.csr_devices.append("si5324_rst_n")
i2c = self.platform.request("i2c") i2c = self.platform.request("i2c")
self.submodules.i2c = gpio.GPIOTristate([i2c.scl, i2c.sda]) self.submodules.i2c = gpio.GPIOTristate([i2c.scl, i2c.sda])
@ -412,7 +412,7 @@ class _SatelliteBase(BaseSoC):
platform.add_false_path_constraints( platform.add_false_path_constraints(
self.crg.cd_sys.clk, self.siphaser.mmcm_freerun_output) self.crg.cd_sys.clk, self.siphaser.mmcm_freerun_output)
self.csr_devices.append("siphaser") self.csr_devices.append("siphaser")
self.submodules.si5324_rst_n = gpio.GPIOOut(platform.request("si5324_33").rst_n) self.submodules.si5324_rst_n = gpio.GPIOOut(platform.request("si5324_33").rst_n, reset_out=1)
self.csr_devices.append("si5324_rst_n") self.csr_devices.append("si5324_rst_n")
i2c = self.platform.request("i2c") i2c = self.platform.request("i2c")
self.submodules.i2c = gpio.GPIOTristate([i2c.scl, i2c.sda]) self.submodules.i2c = gpio.GPIOTristate([i2c.scl, i2c.sda])

14
artiq/gateware/test/drtio/test_full_stack.py
View File

@ -169,7 +169,7 @@ class TestFullStack(unittest.TestCase):
yield from tb.sync() yield from tb.sync()
run_simulation(tb.dut, run_simulation(tb.dut,
{"sys": test()}, self.clocks) {"sys": [test(), tb.check_ttls(ttl_changes)]}, self.clocks)
self.assertEqual(ttl_changes, correct_ttl_changes) self.assertEqual(ttl_changes, correct_ttl_changes)
def test_underflow(self): def test_underflow(self):
@ -214,7 +214,7 @@ class TestFullStack(unittest.TestCase):
yield from tb.sync() yield from tb.sync()
run_simulation(tb.dut, run_simulation(tb.dut,
{"sys": test()}, self.clocks) {"sys": [test(), tb.check_ttls(ttl_changes)]}, self.clocks)
self.assertEqual(ttl_changes, correct_ttl_changes) self.assertEqual(ttl_changes, correct_ttl_changes)
def test_write_underflow(self): def test_write_underflow(self):
@ -227,16 +227,16 @@ class TestFullStack(unittest.TestCase):
errors = yield from saterr.protocol_error.read() errors = yield from saterr.protocol_error.read()
self.assertEqual(errors, 0) self.assertEqual(errors, 0)
yield from csrs.underflow_margin.write(0) yield from csrs.underflow_margin.write(0)
tb.delay(100) tb.delay(80)
yield from tb.write(42, 1) yield from tb.write(42, 1)
for i in range(12): for i in range(21):
yield yield
errors = yield from saterr.protocol_error.read() errors = yield from saterr.protocol_error.read()
underflow_channel = yield from saterr.underflow_channel.read() underflow_channel = yield from saterr.underflow_channel.read()
underflow_timestamp_event = yield from saterr.underflow_timestamp_event.read() underflow_timestamp_event = yield from saterr.underflow_timestamp_event.read()
self.assertEqual(errors, 8) # write underflow self.assertEqual(errors, 8) # write underflow
self.assertEqual(underflow_channel, 42) self.assertEqual(underflow_channel, 42)
self.assertEqual(underflow_timestamp_event, 100) self.assertEqual(underflow_timestamp_event, 80)
yield from saterr.protocol_error.write(errors) yield from saterr.protocol_error.write(errors)
yield yield
errors = yield from saterr.protocol_error.read() errors = yield from saterr.protocol_error.read()
@ -284,7 +284,7 @@ class TestFullStack(unittest.TestCase):
yield dut.phy2.rtlink.i.stb.eq(0) yield dut.phy2.rtlink.i.stb.eq(0)
run_simulation(dut, run_simulation(dut,
{"sys": test()}, self.clocks) {"sys": [test(), generate_input()]}, self.clocks)
def test_echo(self): def test_echo(self):
dut = DUT(2) dut = DUT(2)
@ -303,7 +303,7 @@ class TestFullStack(unittest.TestCase):
yield yield
yield dut.master.rt_packet.echo_stb.eq(0) yield dut.master.rt_packet.echo_stb.eq(0)
for i in range(15): for i in range(17):
yield yield
self.assertEqual((yield dut.master.rt_packet.packet_cnt_tx), 1) self.assertEqual((yield dut.master.rt_packet.packet_cnt_tx), 1)

4
artiq/gateware/test/rtio/test_dma.py
View File

@ -203,11 +203,11 @@ class TestDMA(unittest.TestCase):
run_simulation(tb[32], {"sys": [ run_simulation(tb[32], {"sys": [
do_dma(tb[32].dut, 0), monitor(32), do_dma(tb[32].dut, 0), monitor(32),
(None for _ in range(70)), (None for _ in range(70)),
]}, {"sys": 8, "sys": 8, "rio": 8, "rio_phy": 8}) ]}, {"sys": 8, "rio": 8, "rio_phy": 8})
run_simulation(tb[64], {"sys": [ run_simulation(tb[64], {"sys": [
do_dma(tb[64].dut, 0), monitor(64), do_dma(tb[64].dut, 0), monitor(64),
(None for _ in range(70)), (None for _ in range(70)),
]}, {"sys": 8, "sys": 8, "rio": 8, "rio_phy": 8}) ]}, {"sys": 8, "rio": 8, "rio_phy": 8})
correct_changes = [(timestamp + 11, channel) correct_changes = [(timestamp + 11, channel)
for channel, timestamp, _, _ in test_writes_full_stack] for channel, timestamp, _, _ in test_writes_full_stack]