mirror of https://github.com/m-labs/artiq
216 lines
6.1 KiB
Python
216 lines
6.1 KiB
Python
import unittest
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import random
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import itertools
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from migen import *
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from misoc.interconnect import wishbone
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from artiq.coredevice.exceptions import RTIOUnderflow, RTIODestinationUnreachable
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from artiq.gateware import rtio
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from artiq.gateware.rtio import dma, cri
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from artiq.gateware.rtio.phy import ttl_simple
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def encode_n(n, min_length, max_length):
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r = []
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while n:
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r.append(n & 0xff)
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n >>= 8
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r += [0]*(min_length - len(r))
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if len(r) > max_length:
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raise ValueError
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return r
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def encode_record(channel, timestamp, address, data):
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r = []
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r += encode_n(channel, 3, 3)
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r += encode_n(timestamp, 8, 8)
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r += encode_n(address, 1, 1)
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r += encode_n(data, 1, 64)
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return encode_n(len(r)+1, 1, 1) + r
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def pack(x, size, dw):
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r = []
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for i in range((len(x)+size-1)//size):
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n = 0
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for j in range(i*size//(dw//8), (i+1)*size//(dw//8)):
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n <<= dw
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try:
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encoded = int.from_bytes(x[j*(dw//8): (j+1)*(dw//8)], "little")
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n |= encoded
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except IndexError:
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pass
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r.append(n)
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return r
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def encode_sequence(writes, ws, dw):
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sequence = [b for write in writes for b in encode_record(*write)]
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sequence.append(0)
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return pack(sequence, ws, dw)
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def do_dma(dut, address):
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yield from dut.dma.base_address.write(address)
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yield from dut.enable.write(1)
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yield
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while ((yield from dut.enable.read())):
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yield
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error = yield from dut.cri_master.error.read()
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if error & 1:
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raise RTIOUnderflow
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if error & 2:
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raise RTIODestinationUnreachable
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test_writes1 = [
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(0x01, 0x23, 0x12, 0x33),
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(0x901, 0x902, 0x11, 0xeeeeeeeeeeeeeefffffffffffffffffffffffffffffff28888177772736646717738388488),
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(0x81, 0x288, 0x88, 0x8888)
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]
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test_writes2 = [
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(0x10, 0x10000, 0x20, 0x77),
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(0x11, 0x10001, 0x22, 0x7777),
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(0x12, 0x10002, 0x30, 0x777777),
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(0x13, 0x10003, 0x40, 0x77777788),
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(0x14, 0x10004, 0x50, 0x7777778899),
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]
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prng = random.Random(0)
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class TB(Module):
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def __init__(self, ws, dw):
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sequence1 = encode_sequence(test_writes1, ws, dw)
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sequence2 = encode_sequence(test_writes2, ws, dw)
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offset = 512//ws
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assert len(sequence1) < offset
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sequence = (
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sequence1 +
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[prng.randrange(2**(ws*8)) for _ in range(offset-len(sequence1))] +
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sequence2)
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bus = wishbone.Interface(ws*8)
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self.submodules.memory = wishbone.SRAM(
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1024, init=sequence, bus=bus)
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self.submodules.dut = dma.DMA(bus, dw)
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test_writes_full_stack = [
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(0, 32, 0, 1),
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(1, 40, 0, 1),
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(0, 48, 0, 0),
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(1, 50, 0, 0),
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]
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class FullStackTB(Module):
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def __init__(self, ws, dw):
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self.ttl0 = Signal()
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self.ttl1 = Signal()
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self.submodules.phy0 = ttl_simple.Output(self.ttl0)
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self.submodules.phy1 = ttl_simple.Output(self.ttl1)
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rtio_channels = [
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rtio.Channel.from_phy(self.phy0),
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rtio.Channel.from_phy(self.phy1)
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]
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sequence = encode_sequence(test_writes_full_stack, ws, dw)
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bus = wishbone.Interface(ws*8, 32-log2_int(dw//8))
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self.submodules.memory = wishbone.SRAM(
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256, init=sequence, bus=bus)
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self.submodules.dut = dma.DMA(bus, dw)
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self.submodules.tsc = rtio.TSC()
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self.submodules.rtio = rtio.Core(self.tsc, rtio_channels)
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self.comb += self.dut.cri.connect(self.rtio.cri)
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class TestDMA(unittest.TestCase):
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def test_dma_noerror(self):
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tb = {
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32: TB(64, 32),
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64: TB(64, 64)
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}
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def do_writes(dw):
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yield from do_dma(tb[dw].dut, 0)
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yield from do_dma(tb[dw].dut, 512)
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received = {
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32: [],
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64: []
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}
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@passive
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def rtio_sim(dw):
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dut_cri = tb[dw].dut.cri
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while True:
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cmd = yield dut_cri.cmd
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if cmd == cri.commands["nop"]:
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pass
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elif cmd == cri.commands["write"]:
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channel = yield dut_cri.chan_sel
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timestamp = yield dut_cri.o_timestamp
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address = yield dut_cri.o_address
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data = yield dut_cri.o_data
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received[dw].append((channel, timestamp, address, data))
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yield dut_cri.o_status.eq(1)
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for i in range(prng.randrange(10)):
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yield
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yield dut_cri.o_status.eq(0)
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else:
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self.fail("unexpected RTIO command")
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yield
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run_simulation(tb[32], [do_writes(32), rtio_sim(32)])
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self.assertEqual(received[32], test_writes1 + test_writes2)
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run_simulation(tb[64], [do_writes(64), rtio_sim(64)])
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self.assertEqual(received[64], test_writes1 + test_writes2)
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def test_full_stack(self):
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tb = {
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32: FullStackTB(64, 32),
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64: FullStackTB(64, 64)
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}
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ttl_changes = {
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32: [],
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64: []
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}
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@passive
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def monitor(dw):
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old_ttl_states = [0, 0]
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for time in itertools.count():
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ttl_states = [
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(yield tb[dw].ttl0),
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(yield tb[dw].ttl1)
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]
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for i, (old, new) in enumerate(zip(old_ttl_states, ttl_states)):
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if new != old:
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ttl_changes[dw].append((time, i))
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old_ttl_states = ttl_states
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yield
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run_simulation(tb[32], {"sys": [
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do_dma(tb[32].dut, 0), monitor(32),
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(None for _ in range(70)),
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]}, {"sys": 8, "rio": 8, "rio_phy": 8})
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run_simulation(tb[64], {"sys": [
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do_dma(tb[64].dut, 0), monitor(64),
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(None for _ in range(70)),
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]}, {"sys": 8, "rio": 8, "rio_phy": 8})
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correct_changes = [(timestamp + 11, channel)
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for channel, timestamp, _, _ in test_writes_full_stack]
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self.assertEqual(ttl_changes[32], correct_changes)
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self.assertEqual(ttl_changes[64], correct_changes)
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