mirror of https://github.com/m-labs/artiq
673 lines
27 KiB
Python
Executable File
673 lines
27 KiB
Python
Executable File
#!/usr/bin/env python3
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import argparse
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from migen import *
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from migen.genlib.resetsync import AsyncResetSynchronizer
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from migen.genlib.cdc import MultiReg
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from migen.build.generic_platform import *
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from migen.build.xilinx.vivado import XilinxVivadoToolchain
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from migen.build.xilinx.ise import XilinxISEToolchain
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from misoc.interconnect.csr import *
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from misoc.cores import gpio, timer
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from misoc.targets.kc705 import BaseSoC, MiniSoC, soc_kc705_args, soc_kc705_argdict
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from misoc.integration.builder import builder_args, builder_argdict
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from artiq.gateware.amp import AMPSoC
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from artiq.gateware import rtio, nist_clock, nist_qc2
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from artiq.gateware.rtio.phy import ttl_simple, ttl_serdes_7series, dds, spi2
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from artiq.gateware.rtio.xilinx_clocking import fix_serdes_timing_path
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from artiq.gateware.drtio.transceiver import gtx_7series
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from artiq.gateware.drtio.siphaser import SiPhaser7Series
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from artiq.gateware.drtio.rx_synchronizer import XilinxRXSynchronizer
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from artiq.gateware.drtio import *
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from artiq.build_soc import *
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class SMAClkinForward(Module):
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def __init__(self, platform):
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sma_clkin = platform.request("user_sma_clock")
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sma_clkin_se = Signal()
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sma_clkin_buffered = Signal()
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cdr_clk_se = Signal()
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cdr_clk = platform.request("si5324_clkin_33")
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self.specials += [
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Instance("IBUFDS", i_I=sma_clkin.p, i_IB=sma_clkin.n, o_O=sma_clkin_se),
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Instance("BUFG", i_I=sma_clkin_se, o_O=sma_clkin_buffered),
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Instance("ODDR", i_C=sma_clkin_buffered, i_CE=1, i_D1=0, i_D2=1, o_Q=cdr_clk_se),
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Instance("OBUFDS", i_I=cdr_clk_se, o_O=cdr_clk.p, o_OB=cdr_clk.n)
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]
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# The default voltage for these signals on KC705 is 2.5V, and the Migen platform
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# follows this default. But since the SMAs are on the same bank as the DDS,
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# which is set to 3.3V by reprogramming the KC705 power ICs, we need to
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# redefine them here.
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_reprogrammed3v3_io = [
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("user_sma_gpio_p_33", 0, Pins("Y23"), IOStandard("LVCMOS33")),
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("user_sma_gpio_n_33", 0, Pins("Y24"), IOStandard("LVCMOS33")),
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("si5324_33", 0,
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Subsignal("rst_n", Pins("AE20"), IOStandard("LVCMOS33")),
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Subsignal("int", Pins("AG24"), IOStandard("LVCMOS33"))
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),
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("sfp_tx_disable_n_33", 0, Pins("Y20"), IOStandard("LVCMOS33")),
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# HACK: this should be LVDS, but TMDS is the only supported differential
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# output standard at 3.3V. KC705 hardware design issue?
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("si5324_clkin_33", 0,
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Subsignal("p", Pins("W27"), IOStandard("TMDS_33")),
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Subsignal("n", Pins("W28"), IOStandard("TMDS_33"))
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),
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("sdcard_spi_33", 0,
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Subsignal("miso", Pins("AC20"), Misc("PULLUP=TRUE")),
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Subsignal("clk", Pins("AB23")),
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Subsignal("mosi", Pins("AB22")),
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Subsignal("cs_n", Pins("AC21")),
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IOStandard("LVCMOS33")
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)
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]
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_ams101_dac = [
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("ams101_dac", 0,
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Subsignal("ldac", Pins("XADC:GPIO0")),
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Subsignal("clk", Pins("XADC:GPIO1")),
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Subsignal("mosi", Pins("XADC:GPIO2")),
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Subsignal("cs_n", Pins("XADC:GPIO3")),
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IOStandard("LVTTL")
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)
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]
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class _StandaloneBase(MiniSoC, AMPSoC):
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mem_map = {
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"cri_con": 0x10000000,
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"rtio": 0x20000000,
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"rtio_dma": 0x30000000,
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"mailbox": 0x70000000
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}
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mem_map.update(MiniSoC.mem_map)
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def __init__(self, gateware_identifier_str=None, drtio_100mhz=False, **kwargs):
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MiniSoC.__init__(self,
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cpu_type="vexriscv",
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cpu_bus_width=64,
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sdram_controller_type="minicon",
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l2_size=128*1024,
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integrated_sram_size=8192,
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ethmac_nrxslots=4,
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ethmac_ntxslots=4,
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rtio_sys_merge=True,
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**kwargs)
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AMPSoC.__init__(self)
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add_identifier(self, gateware_identifier_str=gateware_identifier_str)
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if isinstance(self.platform.toolchain, XilinxVivadoToolchain):
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self.platform.toolchain.bitstream_commands.extend([
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"set_property BITSTREAM.GENERAL.COMPRESS True [current_design]",
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])
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if isinstance(self.platform.toolchain, XilinxISEToolchain):
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self.platform.toolchain.bitgen_opt += " -g compress"
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self.platform.add_extension(_reprogrammed3v3_io)
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cdr_clk_out = self.platform.request("si5324_clkout")
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cdr_clk = Signal()
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cdr_clk_buf = Signal()
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self.config["HAS_SI5324"] = None
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self.submodules.si5324_rst_n = gpio.GPIOOut(self.platform.request("si5324_33").rst_n, reset_out=1)
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self.csr_devices.append("si5324_rst_n")
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self.specials += [
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Instance("IBUFDS_GTE2",
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i_CEB=0,
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i_I=cdr_clk_out.p, i_IB=cdr_clk_out.n,
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o_O=cdr_clk,
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p_CLKCM_CFG=1,
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p_CLKRCV_TRST=1,
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p_CLKSWING_CFG="2'b11"),
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Instance("BUFG", i_I=cdr_clk, o_O=cdr_clk_buf)
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]
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self.crg.configure(cdr_clk_buf)
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self.submodules += SMAClkinForward(self.platform)
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self.submodules.timer1 = timer.Timer()
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self.csr_devices.append("timer1")
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self.interrupt_devices.append("timer1")
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self.submodules.leds = gpio.GPIOOut(Cat(
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self.platform.request("user_led", 0),
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self.platform.request("user_led", 1)))
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self.csr_devices.append("leds")
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self.platform.add_extension(_ams101_dac)
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i2c = self.platform.request("i2c")
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self.submodules.i2c = gpio.GPIOTristate([i2c.scl, i2c.sda])
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self.csr_devices.append("i2c")
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self.config["I2C_BUS_COUNT"] = 1
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self.config["HAS_DDS"] = None
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def add_rtio(self, rtio_channels):
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self.submodules.rtio_tsc = rtio.TSC(glbl_fine_ts_width=3)
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self.submodules.rtio_core = rtio.Core(self.rtio_tsc, rtio_channels)
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self.csr_devices.append("rtio_core")
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self.submodules.rtio = rtio.KernelInitiator(self.rtio_tsc)
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self.submodules.rtio_dma = ClockDomainsRenamer("sys_kernel")(
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rtio.DMA(self.get_native_sdram_if(), self.cpu_dw))
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self.register_kernel_cpu_csrdevice("rtio")
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self.register_kernel_cpu_csrdevice("rtio_dma")
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self.submodules.cri_con = rtio.CRIInterconnectShared(
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[self.rtio.cri, self.rtio_dma.cri],
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[self.rtio_core.cri])
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self.register_kernel_cpu_csrdevice("cri_con")
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self.submodules.rtio_moninj = rtio.MonInj(rtio_channels)
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self.csr_devices.append("rtio_moninj")
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self.submodules.rtio_analyzer = rtio.Analyzer(self.rtio_tsc, self.rtio_core.cri,
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self.get_native_sdram_if(), cpu_dw=self.cpu_dw)
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self.csr_devices.append("rtio_analyzer")
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class _MasterBase(MiniSoC, AMPSoC):
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mem_map = {
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"cri_con": 0x10000000,
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"rtio": 0x20000000,
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"rtio_dma": 0x30000000,
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"drtioaux": 0x50000000,
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"mailbox": 0x70000000
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}
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mem_map.update(MiniSoC.mem_map)
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def __init__(self, gateware_identifier_str=None, drtio_100mhz=False, **kwargs):
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clk_freq = 100e6 if drtio_100mhz else 125e6
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MiniSoC.__init__(self,
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cpu_type="vexriscv",
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cpu_bus_width=64,
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sdram_controller_type="minicon",
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l2_size=128*1024,
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integrated_sram_size=8192,
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ethmac_nrxslots=4,
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ethmac_ntxslots=4,
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clk_freq=clk_freq,
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rtio_sys_merge=True,
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**kwargs)
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AMPSoC.__init__(self)
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add_identifier(self, gateware_identifier_str=gateware_identifier_str)
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if isinstance(self.platform.toolchain, XilinxVivadoToolchain):
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self.platform.toolchain.bitstream_commands.extend([
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"set_property BITSTREAM.GENERAL.COMPRESS True [current_design]",
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])
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if isinstance(self.platform.toolchain, XilinxISEToolchain):
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self.platform.toolchain.bitgen_opt += " -g compress"
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platform = self.platform
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platform.add_extension(_reprogrammed3v3_io)
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platform.add_extension(_ams101_dac)
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self.comb += platform.request("sfp_tx_disable_n_33").eq(1)
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data_pads = [
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platform.request("sfp"), platform.request("user_sma_mgt")
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]
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# 1000BASE_BX10 Ethernet compatible, 100/125MHz RTIO clock
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self.submodules.drtio_transceiver = gtx_7series.GTX(
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clock_pads=platform.request("si5324_clkout"),
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pads=data_pads,
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clk_freq=self.clk_freq)
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self.csr_devices.append("drtio_transceiver")
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self.submodules.rtio_tsc = rtio.TSC(glbl_fine_ts_width=3)
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drtio_csr_group = []
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drtioaux_csr_group = []
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drtioaux_memory_group = []
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self.drtio_cri = []
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for i in range(len(self.drtio_transceiver.channels)):
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core_name = "drtio" + str(i)
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coreaux_name = "drtioaux" + str(i)
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memory_name = "drtioaux" + str(i) + "_mem"
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drtio_csr_group.append(core_name)
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drtioaux_csr_group.append(coreaux_name)
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drtioaux_memory_group.append(memory_name)
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cdr = ClockDomainsRenamer({"rtio_rx": "rtio_rx" + str(i)})
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core = cdr(DRTIOMaster(
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self.rtio_tsc, self.drtio_transceiver.channels[i]))
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setattr(self.submodules, core_name, core)
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self.drtio_cri.append(core.cri)
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self.csr_devices.append(core_name)
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coreaux = cdr(DRTIOAuxController(core.link_layer, self.cpu_dw))
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setattr(self.submodules, coreaux_name, coreaux)
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self.csr_devices.append(coreaux_name)
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memory_address = self.mem_map["drtioaux"] + 0x800*i
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self.add_wb_slave(memory_address, 0x800,
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coreaux.bus)
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self.add_memory_region(memory_name, memory_address | self.shadow_base, 0x800)
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self.config["HAS_DRTIO"] = None
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self.config["HAS_DRTIO_ROUTING"] = None
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self.add_csr_group("drtio", drtio_csr_group)
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self.add_csr_group("drtioaux", drtioaux_csr_group)
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self.add_memory_group("drtioaux_mem", drtioaux_memory_group)
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self.config["RTIO_FREQUENCY"] = str(self.drtio_transceiver.rtio_clk_freq/1e6)
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self.submodules.si5324_rst_n = gpio.GPIOOut(platform.request("si5324_33").rst_n, reset_out=1)
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self.csr_devices.append("si5324_rst_n")
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i2c = self.platform.request("i2c")
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self.submodules.i2c = gpio.GPIOTristate([i2c.scl, i2c.sda])
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self.csr_devices.append("i2c")
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self.config["I2C_BUS_COUNT"] = 1
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self.config["HAS_SI5324"] = None
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rtio_clk_period = 1e9/self.drtio_transceiver.rtio_clk_freq
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# Constrain TX & RX timing for the first transceiver channel
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# (First channel acts as master for phase alignment for all channels' TX)
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gtx0 = self.drtio_transceiver.gtxs[0]
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txout_buf = Signal()
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self.specials += Instance("BUFG", i_I=gtx0.txoutclk, o_O=txout_buf)
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self.crg.configure(txout_buf, clk_sw=gtx0.tx_init.done)
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self.comb += [
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platform.request("user_sma_clock_p").eq(ClockSignal("rtio_rx0")),
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platform.request("user_sma_clock_n").eq(gtx0.txoutclk)
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]
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platform.add_period_constraint(gtx0.txoutclk, rtio_clk_period)
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platform.add_period_constraint(gtx0.rxoutclk, rtio_clk_period)
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platform.add_false_path_constraints(
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self.crg.cd_sys.clk, gtx0.rxoutclk)
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# Constrain RX timing for the each transceiver channel
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# (Each channel performs single-lane phase alignment for RX)
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for gtx in self.drtio_transceiver.gtxs[1:]:
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platform.add_period_constraint(gtx.rxoutclk, rtio_clk_period)
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platform.add_false_path_constraints(
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self.crg.cd_sys.clk, gtx.rxoutclk)
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fix_serdes_timing_path(platform)
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def add_rtio(self, rtio_channels):
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self.submodules.rtio_moninj = rtio.MonInj(rtio_channels)
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self.csr_devices.append("rtio_moninj")
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self.submodules.rtio_core = rtio.Core(self.rtio_tsc, rtio_channels)
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self.csr_devices.append("rtio_core")
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self.submodules.rtio = rtio.KernelInitiator(self.rtio_tsc)
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self.submodules.rtio_dma = ClockDomainsRenamer("sys_kernel")(
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rtio.DMA(self.get_native_sdram_if(), self.cpu_dw))
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self.register_kernel_cpu_csrdevice("rtio")
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self.register_kernel_cpu_csrdevice("rtio_dma")
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self.submodules.cri_con = rtio.CRIInterconnectShared(
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[self.rtio.cri, self.rtio_dma.cri],
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[self.rtio_core.cri] + self.drtio_cri,
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enable_routing=True)
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self.register_kernel_cpu_csrdevice("cri_con")
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self.submodules.routing_table = rtio.RoutingTableAccess(self.cri_con)
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self.csr_devices.append("routing_table")
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class _SatelliteBase(BaseSoC):
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mem_map = {
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"drtioaux": 0x50000000,
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}
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mem_map.update(BaseSoC.mem_map)
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def __init__(self, gateware_identifier_str=None, sma_as_sat=False, drtio_100mhz=False, **kwargs):
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clk_freq = 100e6 if drtio_100mhz else 125e6
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BaseSoC.__init__(self,
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cpu_type="vexriscv",
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cpu_bus_width=64,
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sdram_controller_type="minicon",
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l2_size=128*1024,
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integrated_sram_size=8192,
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clk_freq=clk_freq,
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rtio_sys_merge=True,
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**kwargs)
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add_identifier(self, gateware_identifier_str=gateware_identifier_str)
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if isinstance(self.platform.toolchain, XilinxVivadoToolchain):
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self.platform.toolchain.bitstream_commands.extend([
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"set_property BITSTREAM.GENERAL.COMPRESS True [current_design]",
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])
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if isinstance(self.platform.toolchain, XilinxISEToolchain):
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self.platform.toolchain.bitgen_opt += " -g compress"
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platform = self.platform
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platform.add_extension(_reprogrammed3v3_io)
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platform.add_extension(_ams101_dac)
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self.comb += platform.request("sfp_tx_disable_n_33").eq(1)
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data_pads = [
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platform.request("sfp"), platform.request("user_sma_mgt")
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]
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if sma_as_sat:
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data_pads = data_pads[::-1]
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rtio_clk_freq = clk_freq
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# 1000BASE_BX10 Ethernet compatible, 100/125MHz RTIO clock
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self.submodules.drtio_transceiver = gtx_7series.GTX(
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clock_pads=platform.request("si5324_clkout"),
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pads=data_pads,
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clk_freq=self.clk_freq)
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self.csr_devices.append("drtio_transceiver")
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self.submodules.rtio_tsc = rtio.TSC(glbl_fine_ts_width=3)
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drtioaux_csr_group = []
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drtioaux_memory_group = []
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drtiorep_csr_group = []
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self.drtio_cri = []
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for i in range(len(self.drtio_transceiver.channels)):
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coreaux_name = "drtioaux" + str(i)
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memory_name = "drtioaux" + str(i) + "_mem"
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drtioaux_csr_group.append(coreaux_name)
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drtioaux_memory_group.append(memory_name)
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cdr = ClockDomainsRenamer({"rtio_rx": "rtio_rx" + str(i)})
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# Satellite
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if i == 0:
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self.submodules.rx_synchronizer = cdr(XilinxRXSynchronizer())
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core = cdr(DRTIOSatellite(
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self.rtio_tsc, self.drtio_transceiver.channels[0], self.rx_synchronizer))
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self.submodules.drtiosat = core
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self.csr_devices.append("drtiosat")
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# Repeaters
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else:
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corerep_name = "drtiorep" + str(i-1)
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drtiorep_csr_group.append(corerep_name)
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core = cdr(DRTIORepeater(
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self.rtio_tsc, self.drtio_transceiver.channels[i]))
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setattr(self.submodules, corerep_name, core)
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self.drtio_cri.append(core.cri)
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self.csr_devices.append(corerep_name)
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coreaux = cdr(DRTIOAuxController(core.link_layer, self.cpu_dw))
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setattr(self.submodules, coreaux_name, coreaux)
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self.csr_devices.append(coreaux_name)
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memory_address = self.mem_map["drtioaux"] + 0x800*i
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self.add_wb_slave(memory_address, 0x800,
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coreaux.bus)
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self.add_memory_region(memory_name, memory_address | self.shadow_base, 0x800)
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self.config["HAS_DRTIO"] = None
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|
self.config["HAS_DRTIO_ROUTING"] = None
|
|
self.add_csr_group("drtioaux", drtioaux_csr_group)
|
|
self.add_memory_group("drtioaux_mem", drtioaux_memory_group)
|
|
self.add_csr_group("drtiorep", drtiorep_csr_group)
|
|
|
|
self.config["RTIO_FREQUENCY"] = str(self.drtio_transceiver.rtio_clk_freq/1e6)
|
|
# Si5324 Phaser
|
|
self.submodules.siphaser = SiPhaser7Series(
|
|
si5324_clkin=platform.request("si5324_clkin_33"),
|
|
rx_synchronizer=self.rx_synchronizer,
|
|
ref_clk=ClockSignal("bootstrap"),
|
|
ultrascale=False,
|
|
rtio_clk_freq=self.drtio_transceiver.rtio_clk_freq)
|
|
platform.add_false_path_constraints(
|
|
self.crg.cd_sys.clk, self.siphaser.mmcm_freerun_output)
|
|
self.csr_devices.append("siphaser")
|
|
self.submodules.si5324_rst_n = gpio.GPIOOut(platform.request("si5324_33").rst_n, reset_out=1)
|
|
self.csr_devices.append("si5324_rst_n")
|
|
i2c = self.platform.request("i2c")
|
|
self.submodules.i2c = gpio.GPIOTristate([i2c.scl, i2c.sda])
|
|
self.csr_devices.append("i2c")
|
|
self.config["I2C_BUS_COUNT"] = 1
|
|
self.config["HAS_SI5324"] = None
|
|
|
|
rtio_clk_period = 1e9/self.drtio_transceiver.rtio_clk_freq
|
|
# Constrain TX & RX timing for the first transceiver channel
|
|
# (First channel acts as master for phase alignment for all channels' TX)
|
|
gtx0 = self.drtio_transceiver.gtxs[0]
|
|
|
|
txout_buf = Signal()
|
|
self.specials += Instance("BUFG", i_I=gtx0.txoutclk, o_O=txout_buf)
|
|
self.crg.configure(txout_buf, clk_sw=gtx0.tx_init.done)
|
|
|
|
self.comb += [
|
|
platform.request("user_sma_clock_p").eq(ClockSignal("rtio_rx0")),
|
|
platform.request("user_sma_clock_n").eq(gtx0.txoutclk)
|
|
]
|
|
|
|
platform.add_period_constraint(gtx0.txoutclk, rtio_clk_period)
|
|
platform.add_period_constraint(gtx0.rxoutclk, rtio_clk_period)
|
|
# Constrain RX timing for the each transceiver channel
|
|
# (Each channel performs single-lane phase alignment for RX)
|
|
for gtx in self.drtio_transceiver.gtxs[1:]:
|
|
platform.add_period_constraint(gtx.rxoutclk, rtio_clk_period)
|
|
platform.add_false_path_constraints(
|
|
self.crg.cd_sys.clk, gtx.rxoutclk)
|
|
|
|
fix_serdes_timing_path(platform)
|
|
|
|
def add_rtio(self, rtio_channels):
|
|
self.submodules.rtio_moninj = rtio.MonInj(rtio_channels)
|
|
self.csr_devices.append("rtio_moninj")
|
|
|
|
self.submodules.local_io = SyncRTIO(self.rtio_tsc, rtio_channels)
|
|
self.comb += self.drtiosat.async_errors.eq(self.local_io.async_errors)
|
|
self.submodules.cri_con = rtio.CRIInterconnectShared(
|
|
[self.drtiosat.cri],
|
|
[self.local_io.cri] + self.drtio_cri,
|
|
enable_routing=True)
|
|
self.csr_devices.append("cri_con")
|
|
self.submodules.routing_table = rtio.RoutingTableAccess(self.cri_con)
|
|
self.csr_devices.append("routing_table")
|
|
|
|
|
|
class _NIST_CLOCK_RTIO:
|
|
"""
|
|
NIST clock hardware, with old backplane and 11 DDS channels
|
|
"""
|
|
def __init__(self):
|
|
platform = self.platform
|
|
platform.add_extension(nist_clock.fmc_adapter_io)
|
|
|
|
rtio_channels = []
|
|
for i in range(16):
|
|
if i % 4 == 3:
|
|
phy = ttl_serdes_7series.InOut_8X(platform.request("ttl", i))
|
|
self.submodules += phy
|
|
rtio_channels.append(rtio.Channel.from_phy(phy, ififo_depth=512))
|
|
else:
|
|
phy = ttl_serdes_7series.Output_8X(platform.request("ttl", i))
|
|
self.submodules += phy
|
|
rtio_channels.append(rtio.Channel.from_phy(phy))
|
|
|
|
for i in range(2):
|
|
phy = ttl_serdes_7series.InOut_8X(platform.request("pmt", i))
|
|
self.submodules += phy
|
|
rtio_channels.append(rtio.Channel.from_phy(phy, ififo_depth=512))
|
|
|
|
phy = ttl_serdes_7series.InOut_8X(platform.request("user_sma_gpio_n_33"))
|
|
self.submodules += phy
|
|
rtio_channels.append(rtio.Channel.from_phy(phy, ififo_depth=512))
|
|
|
|
phy = ttl_simple.Output(platform.request("user_led", 2))
|
|
self.submodules += phy
|
|
rtio_channels.append(rtio.Channel.from_phy(phy))
|
|
|
|
ams101_dac = self.platform.request("ams101_dac", 0)
|
|
phy = ttl_simple.Output(ams101_dac.ldac)
|
|
self.submodules += phy
|
|
rtio_channels.append(rtio.Channel.from_phy(phy))
|
|
|
|
phy = ttl_simple.ClockGen(platform.request("la32_p"))
|
|
self.submodules += phy
|
|
rtio_channels.append(rtio.Channel.from_phy(phy))
|
|
|
|
phy = spi2.SPIMaster(ams101_dac)
|
|
self.submodules += phy
|
|
rtio_channels.append(rtio.Channel.from_phy(
|
|
phy, ififo_depth=4))
|
|
|
|
for i in range(3):
|
|
phy = spi2.SPIMaster(self.platform.request("spi", i))
|
|
self.submodules += phy
|
|
rtio_channels.append(rtio.Channel.from_phy(
|
|
phy, ififo_depth=128))
|
|
|
|
phy = spi2.SPIMaster(platform.request("sdcard_spi_33"))
|
|
self.submodules += phy
|
|
rtio_channels.append(rtio.Channel.from_phy(
|
|
phy, ififo_depth=4))
|
|
|
|
phy = dds.AD9914(platform.request("dds"), 11, onehot=True)
|
|
self.submodules += phy
|
|
rtio_channels.append(rtio.Channel.from_phy(phy, ififo_depth=4))
|
|
|
|
self.config["HAS_RTIO_LOG"] = None
|
|
self.config["RTIO_LOG_CHANNEL"] = len(rtio_channels)
|
|
rtio_channels.append(rtio.LogChannel())
|
|
|
|
self.add_rtio(rtio_channels)
|
|
|
|
|
|
class _NIST_QC2_RTIO:
|
|
"""
|
|
NIST QC2 hardware, as used in Quantum I and Quantum II, with new backplane
|
|
and 24 DDS channels. Two backplanes are used.
|
|
"""
|
|
def __init__(self):
|
|
platform = self.platform
|
|
platform.add_extension(nist_qc2.fmc_adapter_io)
|
|
|
|
rtio_channels = []
|
|
clock_generators = []
|
|
|
|
# All TTL channels are In+Out capable
|
|
for i in range(40):
|
|
phy = ttl_serdes_7series.InOut_8X(
|
|
platform.request("ttl", i))
|
|
self.submodules += phy
|
|
rtio_channels.append(rtio.Channel.from_phy(phy, ififo_depth=512))
|
|
|
|
# CLK0, CLK1 are for clock generators, on backplane SMP connectors
|
|
for i in range(2):
|
|
phy = ttl_simple.ClockGen(
|
|
platform.request("clkout", i))
|
|
self.submodules += phy
|
|
clock_generators.append(rtio.Channel.from_phy(phy))
|
|
|
|
# user SMA on KC705 board
|
|
phy = ttl_serdes_7series.InOut_8X(platform.request("user_sma_gpio_n_33"))
|
|
self.submodules += phy
|
|
rtio_channels.append(rtio.Channel.from_phy(phy, ififo_depth=512))
|
|
|
|
phy = ttl_simple.Output(platform.request("user_led", 2))
|
|
self.submodules += phy
|
|
rtio_channels.append(rtio.Channel.from_phy(phy))
|
|
|
|
# AMS101 DAC on KC705 XADC header - optional
|
|
ams101_dac = self.platform.request("ams101_dac", 0)
|
|
phy = ttl_simple.Output(ams101_dac.ldac)
|
|
self.submodules += phy
|
|
rtio_channels.append(rtio.Channel.from_phy(phy))
|
|
|
|
# add clock generators after TTLs
|
|
rtio_channels += clock_generators
|
|
|
|
phy = spi2.SPIMaster(ams101_dac)
|
|
self.submodules += phy
|
|
rtio_channels.append(rtio.Channel.from_phy(
|
|
phy, ififo_depth=4))
|
|
|
|
for i in range(4):
|
|
phy = spi2.SPIMaster(self.platform.request("spi", i))
|
|
self.submodules += phy
|
|
rtio_channels.append(rtio.Channel.from_phy(
|
|
phy, ififo_depth=128))
|
|
|
|
for backplane_offset in range(2):
|
|
phy = dds.AD9914(
|
|
platform.request("dds", backplane_offset), 12, onehot=True)
|
|
self.submodules += phy
|
|
rtio_channels.append(rtio.Channel.from_phy(phy, ififo_depth=4))
|
|
|
|
self.config["HAS_RTIO_LOG"] = None
|
|
self.config["RTIO_LOG_CHANNEL"] = len(rtio_channels)
|
|
rtio_channels.append(rtio.LogChannel())
|
|
|
|
self.add_rtio(rtio_channels)
|
|
|
|
|
|
class NIST_CLOCK(_StandaloneBase, _NIST_CLOCK_RTIO):
|
|
def __init__(self, **kwargs):
|
|
_StandaloneBase.__init__(self, **kwargs)
|
|
_NIST_CLOCK_RTIO.__init__(self)
|
|
|
|
|
|
class NIST_QC2(_StandaloneBase, _NIST_QC2_RTIO):
|
|
def __init__(self, **kwargs):
|
|
_StandaloneBase.__init__(self, **kwargs)
|
|
_NIST_QC2_RTIO.__init__(self)
|
|
|
|
|
|
class NIST_CLOCK_Master(_MasterBase, _NIST_CLOCK_RTIO):
|
|
def __init__(self, **kwargs):
|
|
_MasterBase.__init__(self, **kwargs)
|
|
_NIST_CLOCK_RTIO.__init__(self)
|
|
|
|
|
|
class NIST_QC2_Master(_MasterBase, _NIST_QC2_RTIO):
|
|
def __init__(self, **kwargs):
|
|
_MasterBase.__init__(self, **kwargs)
|
|
_NIST_QC2_RTIO.__init__(self)
|
|
|
|
|
|
class NIST_CLOCK_Satellite(_SatelliteBase, _NIST_CLOCK_RTIO):
|
|
def __init__(self, **kwargs):
|
|
_SatelliteBase.__init__(self, **kwargs)
|
|
_NIST_CLOCK_RTIO.__init__(self)
|
|
|
|
|
|
class NIST_QC2_Satellite(_SatelliteBase, _NIST_QC2_RTIO):
|
|
def __init__(self, **kwargs):
|
|
_SatelliteBase.__init__(self, **kwargs)
|
|
_NIST_QC2_RTIO.__init__(self)
|
|
|
|
|
|
VARIANT_CLS = [
|
|
NIST_CLOCK, NIST_QC2,
|
|
NIST_CLOCK_Master, NIST_QC2_Master,
|
|
NIST_CLOCK_Satellite, NIST_QC2_Satellite,
|
|
]
|
|
VARIANTS = {cls.__name__.lower(): cls for cls in VARIANT_CLS}
|
|
|
|
|
|
def main():
|
|
parser = argparse.ArgumentParser(
|
|
description="ARTIQ device binary builder for KC705 systems")
|
|
builder_args(parser)
|
|
soc_kc705_args(parser)
|
|
parser.set_defaults(output_dir="artiq_kc705")
|
|
parser.add_argument("-V", "--variant", default="nist_clock",
|
|
help="variant: "
|
|
"[standalone: nist_clock/nist_qc2] "
|
|
"[DRTIO master: nist_clock_master/nist_qc2_master] "
|
|
"[DRTIO satellite: nist_clock_satellite/nist_qc2_satellite] "
|
|
"(default: %(default)s)")
|
|
parser.add_argument("--gateware-identifier-str", default=None,
|
|
help="Override ROM identifier")
|
|
parser.add_argument("--drtio100mhz", action="store_true", default=False,
|
|
help="DRTIO systems only - use 100MHz RTIO clock")
|
|
args = parser.parse_args()
|
|
|
|
variant = args.variant.lower()
|
|
try:
|
|
cls = VARIANTS[variant]
|
|
except KeyError:
|
|
raise SystemExit("Invalid variant (-V/--variant)")
|
|
|
|
soc = cls(gateware_identifier_str=args.gateware_identifier_str, drtio_100mhz=args.drtio100mhz, **soc_kc705_argdict(args))
|
|
build_artiq_soc(soc, builder_argdict(args))
|
|
|
|
|
|
if __name__ == "__main__":
|
|
main()
|