mirror of https://github.com/m-labs/artiq
189 lines
7.2 KiB
Python
189 lines
7.2 KiB
Python
from types import SimpleNamespace
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from migen import *
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from migen.genlib.resetsync import AsyncResetSynchronizer
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from misoc.interconnect.csr import *
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from artiq.gateware.rtio import cri, rtlink
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from artiq.gateware.rtio.sed.core import *
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from artiq.gateware.rtio.input_collector import *
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from artiq.gateware.drtio import (link_layer,
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rt_packet_satellite, rt_errors_satellite,
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rt_packet_master, rt_controller_master,
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rt_packet_repeater, rt_controller_repeater)
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from artiq.gateware.drtio.rx_synchronizer import GenericRXSynchronizer
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__all__ = ["ChannelInterface", "TransceiverInterface",
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"SyncRTIO",
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"DRTIOSatellite", "DRTIOMaster", "DRTIORepeater"]
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class ChannelInterface:
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def __init__(self, encoder, decoders):
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self.rx_ready = Signal()
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self.encoder = encoder
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self.decoders = decoders
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class TransceiverInterface(AutoCSR):
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def __init__(self, channel_interfaces):
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self.stable_clkin = CSRStorage()
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self.txenable = CSRStorage(len(channel_interfaces))
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for i in range(len(channel_interfaces)):
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name = "rtio_rx" + str(i)
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setattr(self.clock_domains, "cd_"+name, ClockDomain(name=name))
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self.channels = channel_interfaces
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async_errors_layout = [
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("sequence_error", 1),
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("sequence_error_channel", 16),
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("collision", 1),
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("collision_channel", 16),
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("busy", 1),
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("busy_channel", 16)
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]
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class SyncRTIO(Module):
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def __init__(self, tsc, channels, lane_count=8, fifo_depth=128):
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self.cri = cri.Interface()
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self.async_errors = Record(async_errors_layout)
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chan_fine_ts_width = max(max(rtlink.get_fine_ts_width(channel.interface.o)
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for channel in channels),
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max(rtlink.get_fine_ts_width(channel.interface.i)
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for channel in channels))
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assert tsc.glbl_fine_ts_width >= chan_fine_ts_width
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self.submodules.outputs = ClockDomainsRenamer("rio")(
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SED(channels, tsc.glbl_fine_ts_width,
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lane_count=lane_count, fifo_depth=fifo_depth,
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enable_spread=False, report_buffer_space=True,
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interface=self.cri))
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self.comb += self.outputs.coarse_timestamp.eq(tsc.coarse_ts)
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self.sync += self.outputs.minimum_coarse_timestamp.eq(tsc.coarse_ts + 16)
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self.submodules.inputs = ClockDomainsRenamer("rio")(
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InputCollector(tsc, channels, interface=self.cri))
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for attr, _ in async_errors_layout:
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self.comb += getattr(self.async_errors, attr).eq(getattr(self.outputs, attr))
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class DRTIOSatellite(Module):
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def __init__(self, tsc, chanif, rx_synchronizer=None):
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self.reset = CSRStorage(reset=1)
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self.reset_phy = CSRStorage(reset=1)
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self.tsc_loaded = CSR()
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# master interface in the sys domain
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self.cri = cri.Interface()
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self.async_errors = Record(async_errors_layout)
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self.clock_domains.cd_rio = ClockDomain()
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self.clock_domains.cd_rio_phy = ClockDomain()
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self.comb += [
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self.cd_rio.clk.eq(ClockSignal("sys")),
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self.cd_rio_phy.clk.eq(ClockSignal("sys"))
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]
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reset = Signal()
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reset_phy = Signal()
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reset.attr.add("no_retiming")
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reset_phy.attr.add("no_retiming")
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self.sync += [
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reset.eq(self.reset.storage),
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reset_phy.eq(self.reset_phy.storage)
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]
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self.specials += [
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AsyncResetSynchronizer(self.cd_rio, reset),
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AsyncResetSynchronizer(self.cd_rio_phy, reset_phy)
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]
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self.submodules.link_layer = link_layer.LinkLayer(
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chanif.encoder, chanif.decoders)
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self.comb += self.link_layer.rx_ready.eq(chanif.rx_ready)
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if rx_synchronizer is None:
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rx_synchronizer = GenericRXSynchronizer()
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self.submodules += rx_synchronizer
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link_layer_sync = SimpleNamespace(
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tx_aux_frame=self.link_layer.tx_aux_frame,
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tx_aux_data=self.link_layer.tx_aux_data,
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tx_aux_ack=self.link_layer.tx_aux_ack,
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tx_rt_frame=self.link_layer.tx_rt_frame,
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tx_rt_data=self.link_layer.tx_rt_data,
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rx_aux_stb=rx_synchronizer.resync(self.link_layer.rx_aux_stb),
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rx_aux_frame=rx_synchronizer.resync(self.link_layer.rx_aux_frame),
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rx_aux_frame_perm=rx_synchronizer.resync(self.link_layer.rx_aux_frame_perm),
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rx_aux_data=rx_synchronizer.resync(self.link_layer.rx_aux_data),
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rx_rt_frame=rx_synchronizer.resync(self.link_layer.rx_rt_frame),
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rx_rt_frame_perm=rx_synchronizer.resync(self.link_layer.rx_rt_frame_perm),
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rx_rt_data=rx_synchronizer.resync(self.link_layer.rx_rt_data)
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)
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self.submodules.link_stats = link_layer.LinkLayerStats(link_layer_sync, "sys")
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self.submodules.rt_packet = rt_packet_satellite.RTPacketSatellite(
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link_layer_sync, interface=self.cri)
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self.comb += self.rt_packet.reset.eq(self.cd_rio.rst)
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self.comb += [
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tsc.load.eq(self.rt_packet.tsc_load),
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tsc.load_value.eq(self.rt_packet.tsc_load_value)
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]
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self.sync += [
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If(self.tsc_loaded.re, self.tsc_loaded.w.eq(0)),
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If(self.rt_packet.tsc_load, self.tsc_loaded.w.eq(1))
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]
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self.submodules.rt_errors = rt_errors_satellite.RTErrorsSatellite(
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self.rt_packet, tsc, self.async_errors)
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def get_csrs(self):
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return ([self.reset, self.reset_phy, self.tsc_loaded] +
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self.link_layer.get_csrs() + self.link_stats.get_csrs() +
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self.rt_errors.get_csrs())
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class DRTIOMaster(Module):
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def __init__(self, tsc, chanif):
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self.submodules.link_layer = link_layer.LinkLayer(
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chanif.encoder, chanif.decoders)
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self.comb += self.link_layer.rx_ready.eq(chanif.rx_ready)
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self.submodules.link_stats = link_layer.LinkLayerStats(self.link_layer, "rtio_rx")
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self.submodules.rt_packet = rt_packet_master.RTPacketMaster(self.link_layer)
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self.submodules.rt_controller = rt_controller_master.RTController(
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tsc, self.rt_packet)
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def get_csrs(self):
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return (self.link_layer.get_csrs() +
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self.link_stats.get_csrs() +
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self.rt_controller.get_csrs())
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@property
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def cri(self):
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return self.rt_controller.cri
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class DRTIORepeater(Module):
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def __init__(self, tsc, chanif):
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self.submodules.link_layer = link_layer.LinkLayer(
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chanif.encoder, chanif.decoders)
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self.comb += self.link_layer.rx_ready.eq(chanif.rx_ready)
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self.submodules.link_stats = link_layer.LinkLayerStats(self.link_layer, "rtio_rx")
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self.submodules.rt_packet = rt_packet_repeater.RTPacketRepeater(tsc, self.link_layer)
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self.submodules.rt_controller = rt_controller_repeater.RTController(self.rt_packet)
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def get_csrs(self):
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return (self.link_layer.get_csrs() +
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self.link_stats.get_csrs() +
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self.rt_controller.get_csrs())
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@property
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def cri(self):
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return self.rt_packet.cri
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