From eb3742fb08e0b2f1f3b294fd76cf7a51dc42a253 Mon Sep 17 00:00:00 2001 From: mwojcik Date: Mon, 9 Jan 2023 18:15:58 +0800 Subject: [PATCH 1/5] kc705: do not reset si5324 during clock switch --- artiq/gateware/targets/kc705.py | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/artiq/gateware/targets/kc705.py b/artiq/gateware/targets/kc705.py index 4aac6e2ce..a686622b0 100755 --- a/artiq/gateware/targets/kc705.py +++ b/artiq/gateware/targets/kc705.py @@ -113,7 +113,7 @@ class _StandaloneBase(MiniSoC, AMPSoC): self.config["HAS_SI5324"] = None self.config["SI5324_AS_SYNTHESIZER"] = None - self.submodules.si5324_rst_n = gpio.GPIOOut(self.platform.request("si5324_33").rst_n) + self.submodules.si5324_rst_n = gpio.GPIOOut(self.platform.request("si5324_33").rst_n, reset_out=1) self.csr_devices.append("si5324_rst_n") self.specials += [ Instance("IBUFDS_GTE2", @@ -255,7 +255,7 @@ class _MasterBase(MiniSoC, AMPSoC): self.add_memory_group("drtioaux_mem", drtioaux_memory_group) self.config["RTIO_FREQUENCY"] = str(self.drtio_transceiver.rtio_clk_freq/1e6) - self.submodules.si5324_rst_n = gpio.GPIOOut(platform.request("si5324_33").rst_n) + self.submodules.si5324_rst_n = gpio.GPIOOut(platform.request("si5324_33").rst_n, reset_out=1) self.csr_devices.append("si5324_rst_n") i2c = self.platform.request("i2c") self.submodules.i2c = gpio.GPIOTristate([i2c.scl, i2c.sda]) @@ -414,7 +414,7 @@ class _SatelliteBase(BaseSoC): platform.add_false_path_constraints( self.crg.cd_sys.clk, self.siphaser.mmcm_freerun_output) self.csr_devices.append("siphaser") - self.submodules.si5324_rst_n = gpio.GPIOOut(platform.request("si5324_33").rst_n) + self.submodules.si5324_rst_n = gpio.GPIOOut(platform.request("si5324_33").rst_n, reset_out=1) self.csr_devices.append("si5324_rst_n") i2c = self.platform.request("i2c") self.submodules.i2c = gpio.GPIOTristate([i2c.scl, i2c.sda]) From 627504b60e09f9380c2c327928593a205a8a6b0b Mon Sep 17 00:00:00 2001 From: mwojcik Date: Tue, 10 Jan 2023 16:54:45 +0800 Subject: [PATCH 2/5] test_dma: remove redundant clock --- artiq/gateware/test/rtio/test_dma.py | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/artiq/gateware/test/rtio/test_dma.py b/artiq/gateware/test/rtio/test_dma.py index 692e5be17..54b996b4f 100644 --- a/artiq/gateware/test/rtio/test_dma.py +++ b/artiq/gateware/test/rtio/test_dma.py @@ -203,11 +203,11 @@ class TestDMA(unittest.TestCase): run_simulation(tb[32], {"sys": [ do_dma(tb[32].dut, 0), monitor(32), (None for _ in range(70)), - ]}, {"sys": 8, "sys": 8, "rio": 8, "rio_phy": 8}) + ]}, {"sys": 8, "rio": 8, "rio_phy": 8}) run_simulation(tb[64], {"sys": [ do_dma(tb[64].dut, 0), monitor(64), (None for _ in range(70)), - ]}, {"sys": 8, "sys": 8, "rio": 8, "rio_phy": 8}) + ]}, {"sys": 8, "rio": 8, "rio_phy": 8}) correct_changes = [(timestamp + 11, channel) for channel, timestamp, _, _ in test_writes_full_stack] From cd860beda24eac6da418254cdc61db9d83945bae Mon Sep 17 00:00:00 2001 From: mwojcik Date: Tue, 10 Jan 2023 17:09:27 +0800 Subject: [PATCH 3/5] test_full_stack: restore missing check_ttls --- artiq/gateware/test/drtio/test_full_stack.py | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/artiq/gateware/test/drtio/test_full_stack.py b/artiq/gateware/test/drtio/test_full_stack.py index 4c7d367b2..61fb43d2a 100644 --- a/artiq/gateware/test/drtio/test_full_stack.py +++ b/artiq/gateware/test/drtio/test_full_stack.py @@ -169,7 +169,7 @@ class TestFullStack(unittest.TestCase): yield from tb.sync() run_simulation(tb.dut, - {"sys": test()}, self.clocks) + {"sys": [test(), tb.check_ttls(ttl_changes)]}, self.clocks) self.assertEqual(ttl_changes, correct_ttl_changes) def test_underflow(self): @@ -214,7 +214,7 @@ class TestFullStack(unittest.TestCase): yield from tb.sync() run_simulation(tb.dut, - {"sys": test()}, self.clocks) + {"sys": [test(), tb.check_ttls(ttl_changes)]}, self.clocks) self.assertEqual(ttl_changes, correct_ttl_changes) def test_write_underflow(self): @@ -284,7 +284,7 @@ class TestFullStack(unittest.TestCase): yield dut.phy2.rtlink.i.stb.eq(0) run_simulation(dut, - {"sys": test()}, self.clocks) + {"sys": [test(), generate_input()]}, self.clocks) def test_echo(self): dut = DUT(2) From 90424268725a3cda3f34de5aa29670f308f64ce3 Mon Sep 17 00:00:00 2001 From: mwojcik Date: Tue, 10 Jan 2023 17:17:39 +0800 Subject: [PATCH 4/5] echo test: add two more yields --- artiq/gateware/test/drtio/test_full_stack.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/artiq/gateware/test/drtio/test_full_stack.py b/artiq/gateware/test/drtio/test_full_stack.py index 61fb43d2a..e55bb536a 100644 --- a/artiq/gateware/test/drtio/test_full_stack.py +++ b/artiq/gateware/test/drtio/test_full_stack.py @@ -303,7 +303,7 @@ class TestFullStack(unittest.TestCase): yield yield dut.master.rt_packet.echo_stb.eq(0) - for i in range(15): + for i in range(17): yield self.assertEqual((yield dut.master.rt_packet.packet_cnt_tx), 1) From 70edc9c5c61edcf802932bd3fe542d1518f938d7 Mon Sep 17 00:00:00 2001 From: mwojcik Date: Wed, 11 Jan 2023 11:56:21 +0800 Subject: [PATCH 5/5] test_write_underflow: decrease underflow delay --- artiq/gateware/drtio/core.py | 2 +- artiq/gateware/test/drtio/test_full_stack.py | 6 +++--- 2 files changed, 4 insertions(+), 4 deletions(-) diff --git a/artiq/gateware/drtio/core.py b/artiq/gateware/drtio/core.py index 434751ccc..1af7fa7b4 100644 --- a/artiq/gateware/drtio/core.py +++ b/artiq/gateware/drtio/core.py @@ -77,7 +77,7 @@ class DRTIOSatellite(Module): self.reset = CSRStorage(reset=1) self.reset_phy = CSRStorage(reset=1) self.tsc_loaded = CSR() - # master interface in the rtio domain + # master interface in the sys domain self.cri = cri.Interface() self.async_errors = Record(async_errors_layout) diff --git a/artiq/gateware/test/drtio/test_full_stack.py b/artiq/gateware/test/drtio/test_full_stack.py index e55bb536a..ecae7644b 100644 --- a/artiq/gateware/test/drtio/test_full_stack.py +++ b/artiq/gateware/test/drtio/test_full_stack.py @@ -227,16 +227,16 @@ class TestFullStack(unittest.TestCase): errors = yield from saterr.protocol_error.read() self.assertEqual(errors, 0) yield from csrs.underflow_margin.write(0) - tb.delay(100) + tb.delay(80) yield from tb.write(42, 1) - for i in range(12): + for i in range(21): yield errors = yield from saterr.protocol_error.read() underflow_channel = yield from saterr.underflow_channel.read() underflow_timestamp_event = yield from saterr.underflow_timestamp_event.read() self.assertEqual(errors, 8) # write underflow self.assertEqual(underflow_channel, 42) - self.assertEqual(underflow_timestamp_event, 100) + self.assertEqual(underflow_timestamp_event, 80) yield from saterr.protocol_error.write(errors) yield errors = yield from saterr.protocol_error.read()