f3ae8660d0
remove out-of-scope error LED support for satellite
2023-02-17 15:51:38 +08:00
f7f956fc34
panic on sysclk not switched
2023-02-17 15:49:32 +08:00
65678fb4c2
kasli_soc: minor cleanup
2023-02-17 15:34:01 +08:00
02903503c6
libboard_artiq: fix warnings
2023-02-17 15:33:52 +08:00
5f10387684
remove FCLK completely as it's not used
2023-02-17 15:29:46 +08:00
cff2caa88f
zc706: support for 100mhz with new clocking system
2023-02-16 15:09:16 +08:00
ae0d7c807f
use external clock for bootstrap instead of fclk0
2023-02-16 14:52:24 +08:00
39c9ef2940
satman: wait for FCLK, check clk switch
2023-02-16 11:30:44 +08:00
e86923b51d
rtio_clocking: verify clock switch
2023-02-16 11:30:44 +08:00
062fa8e65d
zynq_clocking: export clk switch status
2023-02-16 11:30:44 +08:00
e6b9d5ebcb
set fclk before doing anything else
2023-02-16 11:30:44 +08:00
83d530d8ac
rtio_clocking: init drtio first
2023-02-16 11:30:44 +08:00
aa0760e4ab
kasli_soc: support clock switch on drtio configs
2023-02-16 11:30:44 +08:00
dba8194f09
zc706: cleanup, support for clock switch
2023-02-16 11:30:44 +08:00
0e74afe64f
satman: switch clocks
2023-02-16 11:30:44 +08:00
831079f95f
rtio_clocking: PLL requires a bit more time to lock
2023-02-16 11:30:44 +08:00
ca102d69c3
add fix_serdes_timing_path
2023-02-16 11:30:44 +08:00
ac459617a6
rename clk signals, add "keep" attrs
2023-02-16 11:30:44 +08:00
3194b772ae
move clocking to zynq_clocking
...
add clock-switching FSM
restore order
2023-02-16 11:30:44 +08:00
b26731d83c
flake: update dependencies
2023-02-16 11:30:44 +08:00
1aa6d0a16d
test_dma: remove tsc mode
2023-02-16 11:30:44 +08:00
4aedc2fe61
zc706: fix TSC, PLL parameters
2023-02-16 11:30:44 +08:00
c7e409520a
extract main clock signal from SYSCRG
2023-02-16 11:30:44 +08:00
2cb4285a37
remove removed rtioclockmultiplier
2023-02-16 11:30:44 +08:00
4bf99bc63f
zc706: remove pll_reset
2023-02-16 11:30:44 +08:00
9ac1338a32
test_dma: remove rtio cd
2023-02-16 11:30:44 +08:00
229cef0a07
zc706: change RTIO CRG to SYS
2023-02-16 11:30:44 +08:00
5ab402139c
change init order, avoid providing bootstrap clock
2023-02-16 11:30:44 +08:00
b34f445e55
rtio_clocking: remove unnecessary rtio_crg code
2023-02-16 11:30:44 +08:00
e9d5c41c3d
kasli_soc: merge sys/rtio on standalone
2023-02-16 11:30:44 +08:00
b85c870b82
runtime: drive SFP TX_DISABLE
2023-02-16 10:29:05 +08:00
ca6e0d13ad
Remove virtual LEDs from io_expander
...
Signed-off-by: Egor Savkin <es@m-labs.hk>
2023-02-15 18:14:05 +08:00
b4b7912c40
Port tx_disable-related code from Kasli
...
Signed-off-by: Egor Savkin <es@m-labs.hk>
2023-02-15 17:44:01 +08:00
8230a01701
Build io_expander
...
Signed-off-by: Egor Savkin <es@m-labs.hk>
2023-02-15 15:31:22 +08:00
4bc936f071
Copy io expander from kasli
...
Signed-off-by: Egor Savkin <es@m-labs.hk>
2023-02-15 14:37:55 +08:00
David Nadlinger
df4988c774
rpc: Port over size/alignment fix for structs (tuples) with tail padding
...
This ports over the following commits from the main ARTIQ repo:
- 8740ec3dd52d85084237797881ea137492bfe070
- dbbe8e8ed4f852e623775b7bd3aec818cdd03376
- b9f13d48aa7e2c0652210152b971b21c3c419347
2023-01-28 16:15:28 +00:00
800c12e794
fix resolve_channel_name typing
2023-01-12 16:52:36 +08:00
d36899b485
firmware: unify RTIO error message format
...
Co-authored-by: Egor Savkin <es@m-labs.hk>
Co-committed-by: Egor Savkin <es@m-labs.hk>
2023-01-09 16:13:42 +08:00
6b3fa98d70
add channel names to RTIO errors
...
Co-authored-by: Egor Savkin <es@m-labs.hk>
Co-committed-by: Egor Savkin <es@m-labs.hk>
2023-01-09 12:35:56 +08:00
4a522ecb3b
update ramda and migen-axi
2023-01-06 09:57:56 +08:00
6be5ffe4e4
update flake dependencies
2023-01-06 09:34:15 +08:00
44ef13d1c0
Fix idle/startup_kernel typos in config
...
Signed-off-by: Egor Savkin <es@m-labs.hk>
2023-01-03 09:55:36 +08:00
David Nadlinger
8e0229d265
si5324: crystal_{ref -> as_ckin2} [nfc]
...
This makes it clear that by itself, the flag does not
cause the input mux to be changed.
2022-12-17 01:33:50 +00:00
David Nadlinger
2ddb4d259f
Undo most of Si5324 unification ( 5c054cc901
)
...
This reverts most of 5c054cc901
, as it turns out that
si5324::setup is in fact also used to configure the
chip for operation as a DRTIO satellite.
2022-12-17 01:31:14 +00:00
David Nadlinger
5c054cc901
Unify Si5324 setup code with main ARTIQ repository [nfc]
...
I chose the version from the main repository for two
reasons:
- Explicitly specifying si5324_ref_input every time would
not work for the different Kasli/… hardware versions.
- Having `crystal_ref` as a setting in the configuration
is misleading if it does not actually activate the crystal
for use as a reference (but rather does
`route_crystal_to_ckin2`).
Related m-labs/artiq commits:
- 740543d4e284245248e3ff838c46505938dcae7a
- 3c7a394eff553ab75a7ea78bdd17830366504dc6
2022-12-12 23:22:01 +00:00
c281505aa0
flake: fix cargo hash
2022-12-01 12:49:00 +08:00
db0e41af6d
update zynq-rs and some Rust deps
2022-11-30 22:49:10 +08:00
a07ebb4dc0
flake: nixos 22.11
2022-11-30 22:32:35 +08:00
d5402d899f
flake: update dependencies
2022-10-21 18:57:48 +08:00
bbecead9a3
examples: fix ref_multiplier
2022-10-21 18:53:59 +08:00