0a19f8fb89satman: revert async flag changesmwojcik2024-04-24 17:13:34 +0800
a30c7d1f3aruntime: drtio aux refactoring, revert async flagmwojcik2024-04-24 17:13:21 +0800
2d10503c20libboard_artiq: support multiple aux rx buffersmwojcik2024-04-24 17:12:57 +0800
92a29051f7drtio_aux_controller: support aux_buffer_countmwojcik2024-04-24 17:12:39 +0800
299aa8e775rename `build` derivation to `board-package-set`Florian Agbuya2024-04-23 13:57:13 +0800
14fa038118Firmware: Runtime WRPLL runtime: drive CLK_SEL to true when si549 is used runtime & libboard_artiq: allow standalone to use io_expander si549: add bit bang mmcm dynamic configuration si549: add frequency counter for refclk rtio_clocking & si549: add 125Mhz wrpll refclk setupmorgan2024-03-11 14:46:38 +0800
b81323af30Firmware: Satman skew calibration & tester cargo template: add calibrate_wrpll_skew feature tag collector: add TAG_OFFSET for Satman WRPLL tag collector: add TAG_OFFSET getter & setter for calibration wrpll: add skew tester and calibration wrpll: gate calibration behind calibrate_wrpll_skew featuremorgan2024-03-19 10:36:47 +0800
291777f764Firmware: Satman WRPLL satman: drive CLK_SEL to true when si549 is used satman : add main & helper si549 setup satman : add WRPLL select_recovered_clock si549: add tag collector to process gtx & main tags si549: add frequency counter to set BASE_ADPLL si549: add set_adpll for main & helper PLL si549: add main & helper PLL FIQ & si549: replace dummy with a custom handler for gtx & main tags ISRmorgan2024-04-09 16:32:56 +0800
a1d80fb93bFirmware: Si549 and io_expander io_expander: set CLK_SEL pin to output when si549 is used io_expander: gate virtual leds for standalone si549: add bit bang i2c si549: add si549 programming si549: add main & helper setupmorgan2024-01-04 12:41:36 +0800
7827c7b803Gateware: kasli_soc WRPLL setup kasli_soc: use enable_wrpll from json to switch from si5324 to si549 kasli_soc: add wrpll for all variants kasli_soc: add gtx & main tag nFIQ for all variants kasli_soc: add clk_synth_se for master & satellite kasli_soc: add wrpll_refclk for runtime kasli_soc: add skewtester for satman kasli_soc: add WRPLL_REF_CLK config for firmwaremorgan2024-03-07 13:11:41 +0800
e4d8d44c7cGateware: WRPLL ddmtd: add DDMTD and deglitcher wrpll: add helper clockdomain wrpll: add frequency counter wrpll: add skewtester wrpll: add gtx & main tag collection wrpll: add gtx & main tag eventmanager for shared peripheral interrupt wrpll: add SMA frequency multiplier to generate 125Mhz refclk si549: add i2c and adpll programmermorgan2024-01-04 12:28:40 +0800
7d8268adf2moninj: hold aux mutex for inject for extra time this should prevent gateware errors on satellites
release-7
mwojcik2024-02-28 14:15:50 +0800
e6372b9766zynq_clocking: Allow ext signal to set cur_clk csr - for example, current_clock csr can be connected to tx_init.donelinuswck2023-11-07 15:40:50 +0800
07044752b6zynq_clocking: add ext_async_rst to AsyncRstSYNCRlinuswck2023-11-06 12:24:44 +0800
4a2d9dc597zynq_clocking: Allow ext signal to set cur_clk csr - for example, current_clock csr can be connected to tx_init.donelinuswck2023-11-07 15:40:50 +0800
6573ecd487add has_rtio_moninj cfg to zc706 satellitemorgan2023-11-02 12:36:22 +0800
d507b6f60fzynq_clocking: add ext_async_rst to AsyncRstSYNCRlinuswck2023-11-06 12:24:44 +0800
0e75694c6bfix zc706 master and standalone compilation warning Co-authored-by: morgan <mc@m-labs.hk> Co-committed-by: morgan <mc@m-labs.hk>morgan2023-11-01 17:45:16 +0800
4a34777b97refactor i2c, io_expander, task under the same cfgmorgan2023-10-25 11:52:04 +0800
136e24f597kasli-soc: Add BUFG to the IBUFGDS for MMCM CLKIN1 - Fix Vivado Compilation Error [DRC REQP-119] - MMCME2_ADV CLKIN1 and CLKIN2 are now driven from the same source type (BUFG)linuswck2023-10-11 10:07:06 +0800
174e645736kasli-soc: Add BUFG to the IBUFGDS for MMCM CLKIN1 - Fix Vivado Compilation Error [DRC REQP-119] - MMCME2_ADV CLKIN1 and CLKIN2 are now driven from the same source type (BUFG)linuswck2023-10-11 10:07:06 +0800
a4d1be00c0Firmware: Add drtio_eem.rs support - Port from Artiq repo - Initialize the drtio_eem on main, rtio_clocking - Driver for eem_transceiverlinuswck2023-10-10 10:47:24 +0800
b15322b6bakasli_soc: Add support for shuttler on gateware - Port from artiq repo - Add EEM_DRTIO gatewarelinuswck2023-10-10 10:41:07 +0800
8fd1306145zynq_clocking: Add sys5x, 208MHz CLK & IDELAYCTRL - Port from artiq repo - Generate sys5x for for EEM Serdes, 208MHz REF Clock for IDELAYCTRL - Add IDELAYCTRL for IDEALYE2 in EEM Serdeslinuswck2023-10-05 11:28:45 +0800