test_dma: remove tsc mode
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@ -168,7 +168,7 @@ class FullStackTB(Module):
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bus = axi.Interface(ws*8)
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self.memory = AXIMemorySim(bus, sequence)
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self.submodules.dut = dma.DMA(bus)
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self.submodules.tsc = rtio.TSC("async")
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self.submodules.tsc = rtio.TSC()
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self.submodules.rtio = rtio.Core(self.tsc, rtio_channels)
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self.comb += self.dut.cri.connect(self.rtio.cri)
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