zc706: cleanup, support for clock switch
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0e74afe64f
commit
dba8194f09
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@ -28,49 +28,6 @@ import drtio_aux_controller
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import zynq_clocking
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class SYSCRG(Module, AutoCSR):
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def __init__(self, platform, ps7, main_clk):
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self.pll_locked = CSRStatus()
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self.pll_clksel = CSRStorage()
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self.pll_reset = CSRStorage()
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self.clock_domains.cd_sys = ClockDomain()
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self.clock_domains.cd_sys4x = ClockDomain(reset_less=True)
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pll_locked = Signal()
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sys_clk = Signal()
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sys4x_clk = Signal()
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fb_clk = Signal()
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fclk_buf = Signal()
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self.specials += [
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Instance("BUFG", i_I=ps7.fclk.clk[0], o_O=fclk_buf),
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Instance("PLLE2_ADV",
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p_STARTUP_WAIT="FALSE", o_LOCKED=pll_locked,
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p_BANDWIDTH="HIGH",
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p_REF_JITTER1=0.001,
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p_CLKIN1_PERIOD=8.0, i_CLKIN1=main_clk,
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p_CLKIN2_PERIOD=8.0, i_CLKIN2=fclk_buf,
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i_CLKINSEL=self.pll_clksel.storage,
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# VCO @ 1.5GHz when using 125MHz input
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p_CLKFBOUT_MULT=12, p_DIVCLK_DIVIDE=1,
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i_CLKFBIN=fb_clk,
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i_RST=self.pll_reset.storage,
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o_CLKFBOUT=fb_clk,
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p_CLKOUT0_DIVIDE=12, p_CLKOUT0_PHASE=0.0,
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o_CLKOUT0=sys_clk,
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p_CLKOUT1_DIVIDE=3, p_CLKOUT1_PHASE=0.0,
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o_CLKOUT1=sys4x_clk),
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Instance("BUFG", i_I=sys_clk, o_O=self.cd_sys.clk),
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Instance("BUFG", i_I=sys4x_clk, o_O=self.cd_sys4x.clk),
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AsyncResetSynchronizer(self.cd_sys, ~pll_locked)
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]
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self.comb += self.pll_locked.status.eq(pll_locked)
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platform.add_period_constraint(fclk_buf, 8.)
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platform.add_false_path_constraints(self.cd_sys.clk, fclk_buf, main_clk)
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class SMAClkinForward(Module):
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def __init__(self, platform):
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sma_clkin = platform.request("user_sma_clock")
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@ -173,9 +130,8 @@ class ZC706(SoCCore):
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self.rustc_cfg["si5324_as_synthesizer"] = None
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self.rustc_cfg["si5324_soft_reset"] = None
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self.submodules.sys_crg = SYSCRG(self.platform, self.ps7, cdr_clk_buf)
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self.submodules.sys_crg = zynq_clocking.SYSCRG(self.platform, self.ps7, cdr_clk_buf)
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self.csr_devices.append("sys_crg")
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self.platform.add_period_constraint(self.sys_crg.cd_sys.clk, 8.)
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def add_rtio(self, rtio_channels):
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self.submodules.rtio_tsc = rtio.TSC(glbl_fine_ts_width=3)
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@ -215,20 +171,17 @@ class _MasterBase(SoCCore):
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self.acpki = acpki
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self.rustc_cfg = dict()
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clk_freq = 100e6 if drtio100mhz else 125e6
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platform = zc706.Platform()
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prepare_zc706_platform(platform)
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ident = self.__class__.__name__
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if self.acpki:
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ident = "acpki_" + ident
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SoCCore.__init__(self, platform=platform, csr_data_width=32, ident=ident)
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SoCCore.__init__(self, platform=platform, csr_data_width=32, ident=ident, ps_cd_sys=False)
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platform.add_extension(si5324_fmc33)
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self.sys_clk_freq = 125e6
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rtio_clk_freq = 100e6 if drtio100mhz else self.sys_clk_freq
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platform = self.platform
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self.comb += platform.request("sfp_tx_disable_n").eq(1)
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data_pads = [
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platform.request("sfp"),
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@ -241,11 +194,20 @@ class _MasterBase(SoCCore):
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self.submodules.drtio_transceiver = gtx_7series.GTX(
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clock_pads=platform.request("si5324_clkout"),
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pads=data_pads,
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sys_clk_freq=self.sys_clk_freq,
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rtio_clk_freq=rtio_clk_freq)
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clk_freq=clk_freq)
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self.csr_devices.append("drtio_transceiver")
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self.submodules.rtio_tsc = rtio.TSC(glbl_fine_ts_width=3)
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txout_buf = Signal()
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self.specials += Instance(
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"BUFG",
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i_I=self.drtio_transceiver.gtxs[0].txoutclk,
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o_O=txout_buf)
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self.submodules.sys_crg = zynq_clocking.SYSCRG(
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self.platform,
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self.ps7,
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txout_buf)
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self.csr_devices.append("sys_crg")
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drtio_csr_group = []
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drtioaux_csr_group = []
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@ -288,25 +250,18 @@ class _MasterBase(SoCCore):
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self.rustc_cfg["has_si5324"] = None
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self.rustc_cfg["si5324_as_synthesizer"] = None
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rtio_clk_period = 1e9/self.drtio_transceiver.rtio_clk_freq
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# Constrain TX & RX timing for the first transceiver channel
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# (First channel acts as master for phase alignment for all channels' TX)
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gtx0 = self.drtio_transceiver.gtxs[0]
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platform.add_period_constraint(gtx0.txoutclk, rtio_clk_period)
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platform.add_period_constraint(gtx0.rxoutclk, rtio_clk_period)
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platform.add_false_path_constraints(
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self.ps7.cd_sys.clk,
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gtx0.txoutclk, gtx0.rxoutclk)
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# Constrain RX timing for the each transceiver channel
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# (Each channel performs single-lane phase alignment for RX)
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for gtx in self.drtio_transceiver.gtxs[1:]:
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platform.add_period_constraint(gtx.rxoutclk, rtio_clk_period)
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platform.add_false_path_constraints(
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self.ps7.cd_sys.clk, gtx0.txoutclk, gtx.rxoutclk)
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gtx0.txoutclk, gtx.rxoutclk)
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self.submodules.rtio_crg = RTIOClockMultiplier(self.sys_clk_freq)
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self.csr_devices.append("rtio_crg")
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fix_serdes_timing_path(self.platform)
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fix_serdes_timing_path(platform)
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def add_rtio(self, rtio_channels):
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self.submodules.rtio_tsc = rtio.TSC(glbl_fine_ts_width=3)
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@ -331,7 +286,7 @@ class _MasterBase(SoCCore):
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self.submodules.cri_con = rtio.CRIInterconnectShared(
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[self.rtio.cri, self.rtio_dma.cri],
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[self.rtio_core.cri] + self.drtio_cri,
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mode="sync", enable_routing=True)
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enable_routing=True)
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self.csr_devices.append("cri_con")
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self.submodules.rtio_moninj = rtio.MonInj(rtio_channels)
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@ -350,19 +305,17 @@ class _SatelliteBase(SoCCore):
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self.acpki = acpki
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self.rustc_cfg = dict()
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clk_freq = 100e6 if drtio100mhz else 125e6
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platform = zc706.Platform()
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prepare_zc706_platform(platform)
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ident = self.__class__.__name__
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if self.acpki:
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ident = "acpki_" + ident
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SoCCore.__init__(self, platform=platform, csr_data_width=32, ident=ident)
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SoCCore.__init__(self, platform=platform, csr_data_width=32, ident=ident, ps_cd_sys=False)
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platform.add_extension(si5324_fmc33)
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self.sys_clk_freq = 125e6
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rtio_clk_freq = 100e6 if drtio100mhz else self.sys_clk_freq
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platform = self.platform
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# SFP
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self.comb += platform.request("sfp_tx_disable_n").eq(0)
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data_pads = [
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@ -376,10 +329,21 @@ class _SatelliteBase(SoCCore):
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self.submodules.drtio_transceiver = gtx_7series.GTX(
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clock_pads=platform.request("si5324_clkout"),
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pads=data_pads,
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sys_clk_freq=self.sys_clk_freq,
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rtio_clk_freq=rtio_clk_freq)
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clk_freq=clk_freq)
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self.csr_devices.append("drtio_transceiver")
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txout_buf = Signal()
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txout_buf.attr.add("keep")
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self.specials += Instance(
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"BUFG",
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i_I=self.drtio_transceiver.gtxs[0].txoutclk,
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o_O=txout_buf)
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self.submodules.sys_crg = zynq_clocking.SYSCRG(
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self.platform,
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self.ps7,
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txout_buf)
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self.csr_devices.append("sys_crg")
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drtioaux_csr_group = []
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drtioaux_memory_group = []
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drtiorep_csr_group = []
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@ -437,7 +401,7 @@ class _SatelliteBase(SoCCore):
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ultrascale=False,
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rtio_clk_freq=self.drtio_transceiver.rtio_clk_freq)
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platform.add_false_path_constraints(
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self.ps7.cd_sys.clk, self.siphaser.mmcm_freerun_output)
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self.sys_crg.cd_sys.clk, self.siphaser.mmcm_freerun_output)
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self.csr_devices.append("siphaser")
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self.submodules.si5324_rst_n = gpio.GPIOOut(platform.request("si5324_33").rst_n)
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self.csr_devices.append("si5324_rst_n")
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@ -448,22 +412,15 @@ class _SatelliteBase(SoCCore):
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# Constrain TX & RX timing for the first transceiver channel
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# (First channel acts as master for phase alignment for all channels' TX)
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gtx0 = self.drtio_transceiver.gtxs[0]
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platform.add_period_constraint(gtx0.txoutclk, rtio_clk_period)
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platform.add_period_constraint(gtx0.rxoutclk, rtio_clk_period)
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platform.add_false_path_constraints(
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self.ps7.cd_sys.clk,
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gtx0.txoutclk, gtx0.rxoutclk)
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# Constrain RX timing for the each transceiver channel
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# (Each channel performs single-lane phase alignment for RX)
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for gtx in self.drtio_transceiver.gtxs[1:]:
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platform.add_period_constraint(gtx.rxoutclk, rtio_clk_period)
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platform.add_false_path_constraints(
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self.ps7.cd_sys.clk, gtx.rxoutclk)
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self.sys_crg.cd_sys.clk, gtx.rxoutclk)
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self.submodules.rtio_crg = RTIOClockMultiplier(self.sys_clk_freq)
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self.csr_devices.append("rtio_crg")
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self.rustc_cfg["has_rtio_crg"] = None
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fix_serdes_timing_path(self.platform)
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fix_serdes_timing_path(platform)
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def add_rtio(self, rtio_channels):
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self.submodules.rtio_moninj = rtio.MonInj(rtio_channels)
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@ -485,7 +442,7 @@ class _SatelliteBase(SoCCore):
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self.submodules.cri_con = rtio.CRIInterconnectShared(
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[self.drtiosat.cri],
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[self.local_io.cri] + self.drtio_cri,
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mode="sync", enable_routing=True)
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enable_routing=True)
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self.csr_devices.append("cri_con")
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self.submodules.routing_table = rtio.RoutingTableAccess(self.cri_con)
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