zc706: remove pll_reset

src/gateware/zc706.py

@@ -29,7 +29,6 @@ import drtio_aux_controller
 
 class SYSCRG(Module, AutoCSR):
     def __init__(self, platform):
-        self.pll_reset = CSRStorage(reset=1)
         self.pll_locked = CSRStatus()
         self.clock_domains.cd_sys = ClockDomain()
         self.clock_domains.cd_sys4x = ClockDomain(reset_less=True)
@@ -55,7 +54,7 @@ class SYSCRG(Module, AutoCSR):
                      # VCO @ 1GHz when using 125MHz input
                      p_CLKFBOUT_MULT=8, p_DIVCLK_DIVIDE=1,
                      i_CLKFBIN=self.cd_sys.clk,
-                     i_RST=self.pll_reset.storage,
+                     i_RST=0,
 
                      o_CLKFBOUT=sys_clk,