add fix_serdes_timing_path

src/gateware/kasli_soc.py

@@ -14,6 +14,7 @@ from misoc.integration import cpu_interface
 
 from artiq.coredevice import jsondesc
 from artiq.gateware import rtio, eem_7series
+from artiq.gateware.rtio.xilinx_clocking import fix_serdes_timing_path
 from artiq.gateware.rtio.phy import ttl_simple
 from artiq.gateware.drtio.transceiver import gtx_7series
 from artiq.gateware.drtio.siphaser import SiPhaser7Series
@@ -90,13 +91,13 @@ class GenericStandalone(SoCCore):
                 p_DIFF_TERM="TRUE", p_IBUF_LOW_PWR="FALSE",
                 i_I=clk_synth.p, i_IB=clk_synth.n, o_O=clk_synth_se),
         ]
+        fix_serdes_timing_path(platform)
 
         self.crg = self.ps7 # HACK for eem_7series to find the clock
         self.submodules.sys_crg = zynq_clocking.SYSCRG(self.platform, self.ps7, clk_synth_se)
         self.csr_devices.append("sys_crg")
         # another hack since ps7 itself does not have cd_sys anymore
         self.crg.cd_sys = self.sys_crg.cd_sys
-        self.platform.add_period_constraint(self.sys_crg.cd_sys.clk, 8.)
 
         self.rtio_channels = []
         has_grabber = any(peripheral["type"] == "grabber" for peripheral in description["peripherals"])

src/gateware/zynq_clocking.py

@@ -69,10 +69,10 @@ class SYSCRG(Module, AutoCSR):
         self.clock_domains.cd_sys4x = ClockDomain(reset_less=True)
 
         self.cd_sys.clk.attr.add("keep")
+        self.cd_bootstrap.clk.attr.add("keep")
 
         pll_locked = Signal()
         pll_sys = Signal()
-        pll_sys.attr.add("keep")
         pll_sys4x = Signal()
         fb_clk = Signal()
         fclk_buf = Signal()
@@ -108,5 +108,4 @@ class SYSCRG(Module, AutoCSR):
 
             AsyncResetSynchronizer(self.cd_sys, ~pll_locked | ~ps7.fclk.reset_n[0]),
         ]
-        platform.add_period_constraint(self.cd_bootstrap.clk, 8.)
-        platform.add_false_path_constraints(self.cd_sys.clk, self.cd_bootstrap.clk, main_clk)
+        platform.add_false_path_constraints(self.cd_bootstrap.clk, main_clk)