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27 Commits

Author SHA1 Message Date
mwojcik 38088cea87 cleanup, less unnecessary comments and dup code 2021-10-01 15:35:00 +02:00
mwojcik 45b9d50e70 gateware: fixed zc706/kasli-soc master typos 2021-09-23 14:54:49 +02:00
mwojcik bb5af4f156 gateware: fixing up master classes 2021-09-23 14:22:30 +02:00
mwojcik 176e370872 kasli_soc satellite: fixed rust config 
si5324: fixed double mut borrow in soft reset
 2021-09-13 15:36:47 +02:00
mwojcik 9c09216281 updated gateware for not yet published migen-axi changes 2021-09-13 15:06:34 +02:00
mwojcik d3152f3d24 changed auxctrl tx/rx memory to axi2csr_sram 2021-09-10 15:25:05 +02:00
mwojcik 9c14694fc4 added rtioclockmultiplier where applicable 
(nist variants don't compile for other reasons now)
 2021-09-07 15:22:01 +02:00
mwojcik 1bddad6ff2 kasli_soc: fixes to make satellite variant work 2021-09-07 14:51:46 +02:00
mwojcik 20681a13c4 gateware: fixed cfg keys - case consistent w/ code 2021-09-06 10:57:42 +02:00
mwojcik 0c259d9833 kasli_soc: satellite brought to the same level as zc706 2021-09-03 11:05:41 +02:00
mwojcik 7ff59f57a9 gateware: updated gtx interface 2021-08-10 15:11:21 +02:00
mwojcik d68cf7dd49 gateware: replaced wb slave w/ axi (diff soccore) 2021-08-06 11:05:49 +02:00
mwojcik f9860a61b7 sys_clk_freq is actually 125mhz 2021-08-06 10:39:37 +02:00
mwojcik d1705113aa kasli: gtx transcvr expects separate tx/rx pads 2021-08-06 10:05:45 +02:00
mwojcik 97dfa07bdb determined probable sys_clk_freq for GTX transcvr 2021-08-06 10:05:04 +02:00
mwojcik ecc8a0ccc0 kasli-soc: qpll is not part of this board, removed mentions 2021-08-04 16:44:08 +02:00
mwojcik b95692548e Merge branch 'master' into drtio_port 2021-08-04 09:38:08 +02:00
mwojcik e3d3cb2311 si5324: bring on par with mainline ARTIQ (#132) 
si5324 driver in runtime should be now equal in function to the one in artiq.

kasli-soc has no way of doing a hard reset on the peripheral, but zc706 does.

Reviewed-on: M-Labs/artiq-zynq#132
Co-authored-by: mwojcik <mw@m-labs.hk>
Co-committed-by: mwojcik <mw@m-labs.hk>
 2021-08-04 09:12:38 +08:00
mwojcik 6a9729bede Merge branch 'master' into drtio_port 2021-08-03 09:56:14 +02:00
mwojcik 3ba7fe1e6b kasli_soc uses gtx transceiver instead of gtp 2021-07-30 12:52:58 +02:00
Sebastien Bourdeauducq 8128dc0b56 Revert "kasli-soc: work around I2C breakage (#130)" 
This reverts commit f1fd55dee5.
 2021-07-30 16:55:06 +08:00
mwojcik 248530faf1 gateware: kasli_soc - first attempt at drtio 2021-07-29 13:41:02 +02:00
Sebastien Bourdeauducq 852123b42a kasli-soc: add RTIO LEDs 2021-05-30 20:40:53 +08:00
Sebastien Bourdeauducq f1fd55dee5 kasli-soc: work around I2C breakage (#130) 2021-05-29 17:13:41 +08:00
Sebastien Bourdeauducq 8815f76114 kasli_soc: fix has_grabber 2021-02-15 21:41:02 +08:00
Sebastien Bourdeauducq ef18fa4c6d kasli_soc: add RTIO log channel 2021-02-15 19:56:59 +08:00
Sebastien Bourdeauducq faf9714e10 add demo build for Kasli-SoC 2021-02-15 19:52:13 +08:00