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gateware: fixed zc706/kasli-soc master typos

drtio_port
mwojcik 2021-09-23 14:54:49 +02:00
parent bb5af4f156
commit 45b9d50e70
2 changed files with 10 additions and 12 deletions
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16
src/gateware/kasli_soc.py
View File

@ -208,7 +208,6 @@ class GenericStandalone(SoCCore):
class GenericMaster(SoCCore):
def __init__(self, description, acpki=False):
sys_clk_freq = 125e6
@ -283,11 +282,11 @@ class GenericMaster(SoCCore):
coreaux = cdr(aux_controller.DRTIOAuxControllerBare(core.link_layer))
setattr(self.submodules, coreaux_name, coreaux)
self.csr_devices.append(coreaux_name)
mem_size = coreaux.get_mem_size()
memory_address, size = self.axi2csr.add_port(coreaux.get_tx_port(), mem_size)
size = coreaux.get_mem_size()
memory_address = self.axi2csr.register_port(coreaux.get_tx_port(), size)
# rcv in upper half of the memory, thus added second
self.axi2csr.add_prot(coreaux.get_rx_port(), mem_size)
self.axi2csr.register_port(coreaux.get_rx_port(), size)
self.add_memory_region(memory_name, self.mem_map["csr"] + memory_address, size * 2)
self.rustc_cfg["has_drtio"] = None
self.rustc_cfg["has_drtio_routing"] = None
@ -315,7 +314,8 @@ class GenericMaster(SoCCore):
self.submodules.cri_con = rtio.CRIInterconnectShared(
[self.rtio.cri, self.rtio_dma.cri],
[self.rtio_core.cri])
[self.rtio_core.cri] + self.drtio_cri,
enable_routing=True)
self.csr_devices.append("cri_con")
self.submodules.rtio_moninj = rtio.MonInj(self.rtio_channels)
@ -337,11 +337,9 @@ class GenericMaster(SoCCore):
class GenericSatellite(SoCCore):
def __init__(self, description, acpki=False):
sys_clk_freq = 125e6
rtio_clk_freq = 125e6 # same thing as with master - pulled from desc?
# will probably be replaced with rtio_config key as per #1735
rtio_clk_freq = 125e6
self.acpki = acpki
self.rustc_cfg = dict()

6
src/gateware/zc706.py
View File

@ -229,7 +229,7 @@ class _MasterBase(SoCCore):
drtio_csr_group = []
drtioaux_csr_group = []
drtioaux_memory_group = []
drtio_cri = []
self.drtio_cri = []
for i in range(len(self.drtio_transceiver.channels)):
core_name = "drtio" + str(i)
coreaux_name = "drtioaux" + str(i)
@ -243,7 +243,7 @@ class _MasterBase(SoCCore):
core = cdr(DRTIOMaster(
self.rtio_tsc, self.drtio_transceiver.channels[i]))
setattr(self.submodules, core_name, core)
drtio_cri.append(core.cri)
self.drtio_cri.append(core.cri)
self.csr_devices.append(core_name)
coreaux = cdr(aux_controller.DRTIOAuxControllerBare(core.link_layer))
@ -308,7 +308,7 @@ class _MasterBase(SoCCore):
self.submodules.local_io = SyncRTIO(self.rtio_tsc, rtio_channels)
self.submodules.cri_con = rtio.CRIInterconnectShared(
[self.drtiosat.cri],
[self.rtio.cri, self.rtio_dma.cri],
[self.local_io.cri] + self.drtio_cri,
mode="sync", enable_routing=True)
self.csr_devices.append("cri_con")