4168eb63a7
GIC: fix wrong core target config when enabling interrupt ( #109 )
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# Summary
- Before the patch, an extra 1 is added to `target_cpu` and the interrupt will be configured to the wrong CPU target.
| target_cpu | bits set before patch | bits set after patch |
| -----------| ----------- | ----------- |
| core0 | 0b10 (enable interrupt on core1) | 0b01 (enable interrupt on core0) |
| core1 | 0b11 (enable interrupt on core0 & core1)| 0b10 (enable interrupt on core1) |
- [Correct ICDIPTR Register configuration from AMD](https://docs.xilinx.com/r/en-US/ug585-zynq-7000-SoC-TRM/Software-Generated-Interrupts-SGI?tocId=0TsxAmy8MHRPDsayG96K1Q )
Reviewed-on: M-Labs/zynq-rs#109
Co-authored-by: morgan <mc@m-labs.hk>
Co-committed-by: morgan <mc@m-labs.hk>
2023-12-19 18:41:03 +08:00
0106430805
remove gpio reset
2023-10-18 17:33:19 +08:00
jmatyas
c15b54f92b
kasli-soc: add support for PHY_RST GPIO
2023-08-31 12:58:59 +02:00
0a3a777652
Fix soft_rst bit, add reboot function
2022-10-07 12:57:56 +08:00
42cc256812
add error led
2022-08-26 17:22:42 +08:00
1c8e2c318c
eth phy: reset page to 0 on kasli-soc for ident
2022-03-10 17:11:41 +08:00
c4c52c33b4
eth phy: use unreachable!() for impossible values
2022-03-10 16:45:29 +08:00
072fd5f015
eth phy: set LEDs only on Kasli-SoC
2022-03-10 16:42:25 +08:00
2b3c7e4b2f
eth leds:
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* break led0 from led1 - similar, but not the same settings (led2 not implemented)
* fix values, make it compilable
* set default behavior (one led for link, other for activity)
2022-03-10 16:42:25 +08:00
84d6d391ce
libboard_zynq: eth phy for Marvell 88E1518
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* add support for LED control registers
* support for registers on different pages
2022-03-10 16:42:25 +08:00
3e95df1f64
pca954x_select: api supports no channel enabled
2022-02-11 13:46:51 +08:00
26ab2927b9
pca954x: log detected type
2022-02-11 12:00:39 +08:00
dacc816eb4
pca954x: improve code, fix I2C_SW_RESET behavior
2022-02-11 11:22:53 +08:00
14b0247716
pca954x: fix to work on cold boot
2022-02-09 17:23:33 +08:00
bc41b91192
adjust pca address
2022-02-08 16:39:12 +08:00
3efc682bd6
add pca954x autodetection, pca9547 support
2022-02-08 15:40:17 +08:00
2c161720fa
revert a11cb852a8
2021-07-05 13:45:22 +08:00
a42e5a95ff
phy: fix issue 78, scan PHY MDIO addr starting at 0
2021-07-05 13:25:22 +08:00
b0ec74d764
i2c: half_period -> unit_delay
2021-06-25 16:26:53 +08:00
4159aab6c8
i2c: conservative timing, avoid SCL/SDA races. Closes #83
2021-06-25 16:26:04 +08:00
d18c77c0eb
i2c: fix error messages
2021-06-25 16:23:50 +08:00
411eebd96c
i2c: configure I2C_SW_RESET MIO on Kasli-SoC
2021-06-19 18:49:51 +08:00
a11cb852a8
libboard_zynq: work around Kasli-SoC MDIO breakage ( #78 )
2021-05-29 12:50:28 +08:00
1cd4056370
libboard_zynq: remove unused eth phy name information
2020-11-20 17:21:38 +01:00
ddff295ae1
libboard_zynq: implement eth hot-plugging
2020-11-20 17:12:22 +01:00
379b6b973a
libboard_zynq: add support for target_kasli_soc's Marvell88E1512 eth phy
2020-11-19 20:38:10 +01:00
3172aba1a8
libboard_zynq: improve i2c doc
2020-11-19 20:26:48 +01:00
975202a653
libboard_zynq: enable i2c+eeprom for target_kasli_soc
2020-11-19 20:17:36 +01:00
a3eabf1947
libboard_zynq: prepare target_kasli_soc
2020-11-19 19:28:17 +01:00
a32d7abb9a
libboard_zynq: rename ddr DCI_FREQ to DCI_MAX_FREQ
2020-11-19 19:21:38 +01:00
0714162113
rename target_cora_z7_10 to target_coraz7 globally
2020-11-13 17:56:47 +01:00
5b2c779cba
libboard_zynq: delint ps7_init
2020-11-13 00:23:56 +01:00
0a40d4f36d
libboard_zynq: fix zc706 build
2020-11-13 00:23:38 +01:00
55f8d02da8
libboard_zynq: remove ddr-only ps7_init for redpitaya
2020-11-13 00:12:43 +01:00
990fa56d6a
libboard_zynq: complete ddr without ps7_init for redpitaya
2020-11-13 00:10:34 +01:00
8fd317d580
libboard_zynq: remove ps7_init for cora_z7_10
2020-11-11 14:21:48 +01:00
07fedddad9
libboard_zynq: doc ddr size limitation, correct target_redpitaya to 512MB
2020-11-11 13:25:55 +01:00
dffe3cb251
libboard_zynq: rm superfluous ddr settings for cora_z7_10
2020-11-10 20:53:46 +01:00
b9323653bb
libboard_zynq: complete ddr without ps7_init for cora_z7_10
2020-11-10 14:33:31 +01:00
515d3bb381
libboard_zynq: configure ddr while keeping rstb low
2020-11-08 22:47:59 +01:00
7e22010d7d
libboard_zynq: fix pll_cp/pll_res swap in ClockSource::setup()
2020-11-08 22:46:43 +01:00
9ee77d8f44
libboard_zynq: indent ps7_init/cora_z7_10
2020-11-08 19:32:31 +01:00
e508b78b3e
libboard_zynq: add ps7_init for cora_z7_10
2020-11-08 19:28:59 +01:00
f60d0589cc
fix ps7_init compilation error and warnings
2020-10-01 00:17:47 +08:00
c336e450b1
libboard_zynq/eth/phy: add PEF7071
2020-09-29 16:01:54 +08:00
6af453494b
libboard_zynq/ddr: use ps7_init for redpitaya ddr
2020-09-26 17:01:37 +08:00
e601ac9c45
remove flash support
...
PITA to get to work and most boards have SD.
2020-09-09 20:13:13 +08:00
a6955edf14
add Red Pitaya support (WIP)
2020-09-09 20:10:05 +08:00
ae244082ed
more cpu options
2020-09-07 16:13:51 +08:00
66c66447dd
fix some compilation warnings
2020-09-06 00:17:59 +08:00
