forked from M-Labs/zynq-rs
rename target_cora_z7_10 to target_coraz7 globally
This commit is contained in:
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5b2c779cba
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0714162113
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@ -38,7 +38,7 @@ openocd -f zc706.cfg
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### Running on the Cora Z7-10
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```shell
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nix-shell --command "cd experiments && cargo xbuild --release --no-default-features --features=target_cora_z7_10"
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nix-shell --command "cd experiments && cargo xbuild --release --no-default-features --features=target_coraz7"
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cd openocd
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openocd -f cora-z7-10.cfg
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```
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@ -7,7 +7,7 @@ edition = "2018"
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[features]
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target_zc706 = ["libboard_zynq/target_zc706", "libsupport_zynq/target_zc706"]
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target_cora_z7_10 = ["libboard_zynq/target_cora_z7_10", "libsupport_zynq/target_cora_z7_10"]
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target_coraz7 = ["libboard_zynq/target_coraz7", "libsupport_zynq/target_coraz7"]
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target_redpitaya = ["libboard_zynq/target_redpitaya", "libsupport_zynq/target_redpitaya"]
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default = ["target_zc706"]
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@ -107,7 +107,7 @@ pub fn main_core0() {
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#[cfg(feature = "target_zc706")]
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const CPU_FREQ: u32 = 800_000_000;
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#[cfg(feature = "target_cora_z7_10")]
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#[cfg(feature = "target_coraz7")]
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const CPU_FREQ: u32 = 650_000_000;
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#[cfg(feature = "target_redpitaya")]
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const CPU_FREQ: u32 = 800_000_000;
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@ -120,7 +120,7 @@ pub fn main_core0() {
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IoPll::setup(1_000_000_000);
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libboard_zynq::stdio::drop_uart();
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}
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#[cfg(feature = "target_cora_z7_10")]
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#[cfg(feature = "target_coraz7")]
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{
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IoPll::setup(1_000_000_000);
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libboard_zynq::stdio::drop_uart();
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@ -7,7 +7,7 @@ edition = "2018"
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[features]
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target_zc706 = []
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target_cora_z7_10 = []
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target_coraz7 = []
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target_redpitaya = []
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ipv6 = [ "smoltcp/proto-ipv6" ]
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@ -4,7 +4,7 @@ use super::slcr;
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#[cfg(feature = "target_zc706")]
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pub const PS_CLK: u32 = 33_333_333;
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#[cfg(feature = "target_cora_z7_10")]
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#[cfg(feature = "target_coraz7")]
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pub const PS_CLK: u32 = 50_000_000;
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#[cfg(feature = "target_redpitaya")]
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pub const PS_CLK: u32 = 33_333_333;
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@ -12,7 +12,7 @@ mod regs;
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/// Micron MT41J256M8HX-15E: 667 MHz DDR3
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const DDR_FREQ: u32 = 666_666_666;
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#[cfg(feature = "target_cora_z7_10")]
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#[cfg(feature = "target_coraz7")]
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/// Micron MT41K256M16HA-125: 800 MHz DDR3L, max supported 533 MHz
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const DDR_FREQ: u32 = 525_000_000;
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@ -144,13 +144,13 @@ impl DdrRam {
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.output_en(slcr::DdriobOutputEn::Obuf);
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#[cfg(feature = "target_zc706")]
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let data1_config = data0_config.clone();
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#[cfg(feature = "target_cora_z7_10")]
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#[cfg(feature = "target_coraz7")]
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let data0_config = slcr::DdriobConfig::zeroed()
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.inp_type(slcr::DdriobInputType::VrefDifferential)
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.term_en(true)
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.dci_type(slcr::DdriobDciType::Termination)
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.output_en(slcr::DdriobOutputEn::Obuf);
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#[cfg(feature = "target_cora_z7_10")]
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#[cfg(feature = "target_coraz7")]
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let data1_config = slcr::DdriobConfig::zeroed()
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.pullup_en(true);
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#[cfg(feature = "target_redpitaya")]
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@ -173,13 +173,13 @@ impl DdrRam {
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.output_en(slcr::DdriobOutputEn::Obuf);
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#[cfg(feature = "target_zc706")]
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let diff1_config = diff0_config.clone();
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#[cfg(feature = "target_cora_z7_10")]
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#[cfg(feature = "target_coraz7")]
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let diff0_config = slcr::DdriobConfig::zeroed()
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.inp_type(slcr::DdriobInputType::Differential)
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.term_en(true)
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.dci_type(slcr::DdriobDciType::Termination)
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.output_en(slcr::DdriobOutputEn::Obuf);
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#[cfg(feature = "target_cora_z7_10")]
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#[cfg(feature = "target_coraz7")]
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let diff1_config = slcr::DdriobConfig::zeroed()
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.pullup_en(true);
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#[cfg(feature = "target_redpitaya")]
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@ -207,7 +207,7 @@ impl DdrRam {
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slcr.ddriob_drive_slew_clock.write(0x00F9861C);
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}
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#[cfg(feature = "target_cora_z7_10")]
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#[cfg(feature = "target_coraz7")]
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slcr.ddriob_ddr_ctrl.modify(|_, w| w
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.vref_int_en(false)
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.vref_ext_en_lower(true)
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@ -232,7 +232,7 @@ impl DdrRam {
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}
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fn configure(&mut self) {
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#[cfg(feature = "target_cora_z7_10")]
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#[cfg(feature = "target_coraz7")]
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self.regs.dram_param0.write(
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regs::DramParam0::zeroed()
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.t_rc(0x1a)
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@ -295,11 +295,11 @@ impl DdrRam {
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.emr(0x4)
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);
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#[cfg(feature = "target_cora_z7_10")]
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#[cfg(feature = "target_coraz7")]
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self.regs.phy_configs[2].modify(
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|_, w| w.data_slice_in_use(false)
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);
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#[cfg(feature = "target_cora_z7_10")]
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#[cfg(feature = "target_coraz7")]
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self.regs.phy_configs[3].modify(
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|_, w| w.data_slice_in_use(false)
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);
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@ -351,7 +351,7 @@ impl DdrRam {
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.gatelvl_init_ratio(0xee)
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);
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#[cfg(feature = "target_cora_z7_10")]
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#[cfg(feature = "target_coraz7")]
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self.regs.reg_64.modify(
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|_, w| w
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.phy_ctrl_slave_ratio(0x100)
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@ -387,7 +387,7 @@ impl DdrRam {
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fn reset_ddrc<F: FnMut(&mut Self)>(&mut self, mut f: F) {
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#[cfg(feature = "target_zc706")]
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let width = regs::DataBusWidth::Width32bit;
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#[cfg(feature = "target_cora_z7_10")]
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#[cfg(feature = "target_coraz7")]
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let width = regs::DataBusWidth::Width16bit;
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#[cfg(feature = "target_redpitaya")]
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let width = regs::DataBusWidth::Width16bit;
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@ -405,7 +405,7 @@ impl DdrRam {
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self.regs.dram_addr_map_col.write(0xFFF00000);
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self.regs.dram_addr_map_row.write(0x0F666666);
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}
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#[cfg(any(feature = "target_cora_z7_10", feature = "target_redpitaya"))]
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#[cfg(any(feature = "target_coraz7", feature = "target_redpitaya"))]
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unsafe {
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// row/column address bits
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self.regs.dram_addr_map_bank.write(0x00000666);
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@ -437,7 +437,7 @@ impl DdrRam {
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// filtering address map
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#[cfg(feature = "target_zc706")]
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let megabytes = 1023;
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#[cfg(feature = "target_cora_z7_10")]
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#[cfg(feature = "target_coraz7")]
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let megabytes = 512;
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#[cfg(feature = "target_redpitaya")]
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let megabytes = 512;
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@ -105,7 +105,7 @@ impl Sdio {
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);
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}
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// cora card detect pin
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#[cfg(feature = "target_cora_z7_10")]
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#[cfg(feature = "target_coraz7")]
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{
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unsafe {
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slcr.sd0_wp_cd_sel.write(47 << 16);
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@ -45,7 +45,7 @@ impl DerefMut for LazyUart {
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fn deref_mut(&mut self) -> &mut Uart {
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match self {
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LazyUart::Uninitialized => {
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#[cfg(any(feature = "target_cora_z7_10", feature = "target_redpitaya"))]
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#[cfg(any(feature = "target_coraz7", feature = "target_redpitaya"))]
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let uart = Uart::uart0(UART_RATE);
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#[cfg(feature = "target_zc706")]
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let uart = Uart::uart1(UART_RATE);
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@ -13,7 +13,7 @@ pub struct Uart {
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}
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impl Uart {
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#[cfg(any(feature = "target_cora_z7_10", feature = "target_redpitaya"))]
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#[cfg(any(feature = "target_coraz7", feature = "target_redpitaya"))]
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pub fn uart0(baudrate: u32) -> Self {
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slcr::RegisterBlock::unlocked(|slcr| {
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// Route UART 0 RxD/TxD Signals to MIO Pins
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@ -12,6 +12,6 @@ log = "0.4"
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[features]
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target_zc706 = []
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target_cora_z7_10 = []
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target_coraz7 = []
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target_redpitaya = []
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ipv6 = []
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@ -35,9 +35,9 @@ pub fn get_adresses(cfg: &Config) -> NetAddresses {
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let mut hardware_addr = EthernetAddress([0x02, 0x00, 0x00, 0x00, 0x00, 0x52]);
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#[cfg(feature = "target_zc706")]
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let mut ipv4_addr = IpAddress::v4(192, 168, 1, 52);
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#[cfg(feature = "target_cora_z7_10")]
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#[cfg(feature = "target_coraz7")]
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let mut hardware_addr = EthernetAddress([0x02, 0x00, 0x00, 0x00, 0x00, 0x54]);
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#[cfg(feature = "target_cora_z7_10")]
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#[cfg(feature = "target_coraz7")]
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let mut ipv4_addr = IpAddress::v4(192, 168, 1, 54);
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#[cfg(feature = "target_redpitaya")]
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let mut hardware_addr = EthernetAddress([0x02, 0x00, 0x00, 0x00, 0x00, 0x55]);
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@ -6,7 +6,7 @@ edition = "2018"
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[features]
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target_zc706 = []
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target_cora_z7_10 = []
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target_coraz7 = []
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target_redpitaya = []
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power_saving = []
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default = ["target_zc706"]
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@ -7,7 +7,7 @@ edition = "2018"
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[features]
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target_zc706 = ["libboard_zynq/target_zc706"]
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target_cora_z7_10 = ["libboard_zynq/target_cora_z7_10"]
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target_coraz7 = ["libboard_zynq/target_coraz7"]
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target_redpitaya = ["libboard_zynq/target_redpitaya"]
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panic_handler = []
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dummy_irq_handler = []
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@ -7,7 +7,7 @@ edition = "2018"
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[features]
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target_zc706 = ["libboard_zynq/target_zc706", "libsupport_zynq/target_zc706", "libconfig/target_zc706"]
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target_cora_z7_10 = ["libboard_zynq/target_cora_z7_10", "libsupport_zynq/target_cora_z7_10", "libconfig/target_cora_z7_10"]
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target_coraz7 = ["libboard_zynq/target_coraz7", "libsupport_zynq/target_coraz7", "libconfig/target_coraz7"]
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target_redpitaya = ["libboard_zynq/target_redpitaya", "libsupport_zynq/target_redpitaya", "libconfig/target_redpitaya"]
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default = ["target_zc706"]
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