M-Labs/zynq-rs
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GIC: fix wrong core target config when enabling interrupt #109

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sb10q merged 1 commits from morgan/zynq-rs:irq_fix into master 2023-12-19 18:41:03 +08:00
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morgan commented 2023-12-19 17:20:17 +08:00
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Summary

  • Before the patch, an extra 1 is added to target_cpu and the interrupt will be configured to the wrong CPU target.
target_cpu bits set before patch bits set after patch
core0 0b10 (enable interrupt on core1) 0b01 (enable interrupt on core0)
core1 0b11 (enable interrupt on core0 & core1) 0b10 (enable interrupt on core1)
# Summary - Before the patch, an extra 1 is added to `target_cpu` and the interrupt will be configured to the wrong CPU target. | target_cpu | bits set before patch | bits set after patch | | -----------| ----------- | ----------- | | core0 | 0b10 (enable interrupt on core1) | 0b01 (enable interrupt on core0) | | core1 | 0b11 (enable interrupt on core0 & core1)| 0b10 (enable interrupt on core1) | - [Correct ICDIPTR Register configuration from AMD](https://docs.xilinx.com/r/en-US/ug585-zynq-7000-SoC-TRM/Software-Generated-Interrupts-SGI?tocId=0TsxAmy8MHRPDsayG96K1Q)
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morgan added 1 commit 2023-12-19 17:20:18 +08:00
sb10q commented 2023-12-19 18:40:32 +08:00
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PR title is good but the commit message should follow.

PR title is good but the commit message should follow.
sb10q merged commit 4168eb63a7 into master 2023-12-19 18:41:03 +08:00
morgan deleted branch irq_fix 2024-01-31 11:23:47 +08:00
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Reference: M-Labs/zynq-rs#109
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