forked from M-Labs/zynq-rs
kasli-soc: add support for PHY_RST GPIO
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de42a5d1b2
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@ -13,6 +13,9 @@ mod regs;
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pub mod rx;
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pub mod tx;
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use super::time::Milliseconds;
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use embedded_hal::timer::CountDown;
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/// Size of all the buffers
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pub const MTU: usize = 1536;
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/// Maximum MDC clock
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@ -300,11 +303,18 @@ impl<GEM: Gem> Eth<GEM, (), ()> {
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fn gem_common(macaddr: [u8; 6]) -> Self {
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GEM::setup_clock(TX_1000);
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#[cfg(feature="target_kasli_soc")]
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{
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let mut eth_reset_pin = PhyRst::rst_pin();
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eth_reset_pin.reset();
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}
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let mut inner = EthInner {
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gem: PhantomData,
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link: None,
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};
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inner.init();
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inner.configure(macaddr);
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let phy = Phy::find(&mut inner).expect("phy");
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@ -482,6 +492,70 @@ impl<'a, GEM: Gem> smoltcp::phy::Device<'a> for &mut Eth<GEM, rx::DescList, tx::
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}
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}
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pub struct PhyRst {
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regs: regs::GpioRegisterBlock,
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count_down: super::timer::global::CountDown<Milliseconds>,
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}
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impl PhyRst {
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pub fn rst_pin() -> Self {
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slcr::RegisterBlock::unlocked(|slcr| {
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// Hardware Reset for PHY
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slcr.mio_pin_47.write(
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slcr::MioPin47::zeroed()
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.l3_sel(0b000)
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.io_type(slcr::IoBufferType::Lvcmos18)
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.pullup(true)
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.disable_rcvr(true)
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);
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slcr.gpio_rst_ctrl.reset_gpio();
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});
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Self::eth_reset_common(0xFFFF - 0x8000)
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}
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fn delay_ms(&mut self, ms: u64) {
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self.count_down.start(Milliseconds(ms));
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nb::block!(self.count_down.wait()).unwrap();
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}
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fn eth_reset_common(gpio_output_mask: u16) -> Self {
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let self_ = Self {
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regs: regs::GpioRegisterBlock::regs(),
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count_down: unsafe { super::timer::GlobalTimer::get() }.countdown(),
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};
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// Setup GPIO output mask
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self_.regs.gpio_output_mask.modify(|_, w| {
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w.mask(gpio_output_mask)
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});
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self_.regs.gpio_direction.modify(|_, w| {
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w.phy_rst(true)
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});
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self_
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}
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fn oe(&mut self, oe: bool) {
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self.regs.gpio_output_enable.modify(|_, w| {
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w.phy_rst(oe)
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})
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}
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fn toggle(&mut self, o: bool) {
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self.regs.gpio_output_mask.modify(|_, w| {
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w.phy_rst(o)
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})
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}
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pub fn reset(&mut self) {
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self.toggle(false); // drive phy_rst (active LOW) pin low
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self.oe(true); // enable pin's output
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self.delay_ms(10);
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self.toggle(true);
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}
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}
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struct EthInner<GEM: Gem> {
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gem: PhantomData<GEM>,
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@ -110,6 +110,49 @@ pub struct RegisterBlock {
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pub design_cfg5: RO<u32>,
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}
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pub struct GpioRegisterBlock {
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pub gpio_output_mask: &'static mut OutputMask,
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pub gpio_direction: &'static mut Direction,
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pub gpio_output_enable: &'static mut OutputEnable,
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}
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impl GpioRegisterBlock {
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pub fn regs() -> Self {
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Self {
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gpio_output_mask: OutputMask::new(),
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gpio_direction: Direction::new(),
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gpio_output_enable: OutputEnable::new(),
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}
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}
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}
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register!(gpio_output_mask,
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/// MASK_DATA_1_SW:
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/// Maskable output data for MIO[47:32]
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OutputMask, RW, u32);
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register_at!(OutputMask, 0xE000A008, new);
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register_bit!(gpio_output_mask,
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/// Output for PHY_RST (MIO[47])
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phy_rst, 15);
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register_bits!(gpio_output_mask,
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mask, u16, 16, 31);
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register!(gpio_direction,
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/// DIRM_1:
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/// Direction mode for MIO[53:32]; 0/1 = in/out
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Direction, RW, u32);
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register_at!(Direction, 0xE000A244, new);
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register_bit!(gpio_direction,
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/// Direction for PHY_RST
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phy_rst, 15);
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register!(gpio_output_enable,
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/// OEN_1:
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/// Output enable for MIO[53:32]
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OutputEnable, RW, u32);
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register_at!(OutputEnable, 0xE000A248, new);
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register_bit!(gpio_output_enable,
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/// Output enable for PHY_RST
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phy_rst, 15);
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register_at!(RegisterBlock, 0xE000B000, gem0);
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register_at!(RegisterBlock, 0xE000C000, gem1);
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