apatura-iris
5e5cdf0e67
Update installing.rst
...
The file 99-openocd.rules as downloaded from githubusercontent.com seems to be outdated and does now work on Ubuntu 16.04. The version that ships with OpenOCD has an additional ``TAG+="uaccess"`` in the rules file and works fine. Thus I suggest to use the file that is bundled with OpenOCD.
2018-06-27 08:18:50 +02:00
Sebastien Bourdeauducq
811882943b
artiq_flash: RTM gateware is not required for master variant
2018-06-25 18:28:55 +08:00
Sebastien Bourdeauducq
c750de2955
sayma: add many-port pure DRTIO master
2018-06-25 18:21:22 +08:00
Sebastien Bourdeauducq
84b3d9ecc6
bootloader: also check firmware CRC in SDRAM ( #1065 )
2018-06-23 11:28:12 +08:00
Sebastien Bourdeauducq
68530fde07
sayma: generate 100MHz from Si5324 on standalone and master targets
...
* Allow switching between DRTIO satellite and standalone without
touching the hardware.
* Allow operating standalone and master without an additional RF
signal generator.
2018-06-23 10:44:38 +08:00
whitequark
b6dd9c8bb0
runtime: support builds without RTIO DMA.
...
Fixes #1079 .
2018-06-23 00:56:21 +00:00
whitequark
12fde6d34b
artiq_coremgmt: fix typo.
...
Fixes #1056 .
2018-06-23 00:36:59 +00:00
Sebastien Bourdeauducq
51a5d8dff9
examples: add Kasli SAWG master
2018-06-22 18:57:49 +08:00
Sebastien Bourdeauducq
f87da95e57
jesd204: use jesd clock domain for sysref sampler
...
RTIO domain is still in reset during calibration.
2018-06-22 17:13:01 +08:00
Sebastien Bourdeauducq
76fc63bbf7
jesd204: use separate controls for reset and input buffer disable
2018-06-22 11:38:18 +08:00
Sebastien Bourdeauducq
d9955fee76
jesd204: make sure IOB FF is used to sample SYSREF at FPGA
2018-06-22 11:00:56 +08:00
Sebastien Bourdeauducq
60b22217ce
sayma: set DRTIO master HMC830_REF to 100MHz
2018-06-22 10:10:09 +08:00
Sebastien Bourdeauducq
e6d1726754
sayma: add RTIO log to DRTIO master
2018-06-22 00:05:22 +08:00
Sebastien Bourdeauducq
83428961ad
sayma: add SAWG and JESD to DRTIO master
2018-06-22 00:04:22 +08:00
Sebastien Bourdeauducq
c1db02a351
drtio/gth_ultrascale: disable IBUFDS_GTE3 until stable_clkin
...
Precaution against HMC7043 noise issues.
2018-06-21 22:56:07 +08:00
Sebastien Bourdeauducq
8b3c12e6eb
sayma: clock DRTIO master transceiver from HMC7043
2018-06-21 22:34:44 +08:00
Sebastien Bourdeauducq
de7d64d482
sayma: clock JESD204 from GTP CLK2
...
This frees up GTP CLK1, which is routable to the SFP quads, for DRTIO.
2018-06-21 22:33:53 +08:00
Sebastien Bourdeauducq
b28ff587c5
sayma: add sysref sampler to DRTIO master
2018-06-21 22:28:34 +08:00
Sebastien Bourdeauducq
07bcdfd91e
hmc7043: stricter check of FPGA SYSREF margin
2018-06-21 22:26:49 +08:00
Sebastien Bourdeauducq
e29536351d
drtio: resync SYSREF when TSC is loaded
2018-06-21 17:00:32 +08:00
Sebastien Bourdeauducq
5a2a857a2f
firmware: clean up SYSREF phase management
2018-06-21 16:23:41 +08:00
Sebastien Bourdeauducq
05e908a0fd
hmc7043: align SYSREF with RTIO
2018-06-21 15:54:42 +08:00
Sebastien Bourdeauducq
9741654cad
hmc7043: style
2018-06-21 15:54:42 +08:00
Sebastien Bourdeauducq
45e8263208
hmc7043: do not configure phases during initial init
...
They are determined later on.
2018-06-21 15:54:42 +08:00
whitequark
7cc3da4faf
firmware: do not lose the ".dirty" suffix in build versions.
...
Fixes #1074 .
2018-06-21 05:18:51 +00:00
whitequark
095ee28fd9
runtime: fix size values for bytes and bytearray RPCs.
...
Fixes #1076 .
2018-06-21 00:51:56 +00:00
whitequark
9260cdb2e8
compiler: support conversion of list to bytearray and bytes.
...
Fixes #1077 .
2018-06-21 00:40:45 +00:00
Sebastien Bourdeauducq
5a91f820fd
examples: change Sayma sines frequency to 9MHz
...
Well within Red Pitaya bandwidth.
2018-06-20 22:40:07 +08:00
Sebastien Bourdeauducq
9288301543
examples: add DRTIO sines
2018-06-20 22:39:40 +08:00
Sebastien Bourdeauducq
28fb0fd754
sayma: add SYSREF sampler gateware
2018-06-20 17:48:35 +08:00
Sebastien Bourdeauducq
814d0583db
hmc7043: improve smoothness of sysref phase control
2018-06-20 17:40:48 +08:00
Sebastien Bourdeauducq
9142a5ab8a
rtio: expose coarse timestamp in RTIO and DRTIO satellite cores
2018-06-20 17:39:54 +08:00
Sebastien Bourdeauducq
5272c11704
typo
2018-06-20 17:05:20 +08:00
Sebastien Bourdeauducq
0c32d07e8b
ad9154: new sysref scan
...
Print margins around the pre-defined fixed phase.
Also report error if margins are too small.
The fixed phase is also changed by this commit (the value 88 is
from before the new HMC7043 initialization code, and is probably wrong).
2018-06-20 00:15:58 +08:00
Sebastien Bourdeauducq
4803ca3799
examples/sayma_drtio: add SAWG channels
2018-06-19 23:50:26 +08:00
Sebastien Bourdeauducq
3d0e92aefd
hmc7043: check that chip is disabled at startup
2018-06-19 23:49:17 +08:00
Sebastien Bourdeauducq
740e6863c3
hmc7043: add delay after releasing hardware reset
2018-06-19 23:48:48 +08:00
Sebastien Bourdeauducq
75b6cea52f
sayma: add SAWG to DRTIO satellite
2018-06-19 19:12:10 +08:00
Sebastien Bourdeauducq
eb3259b847
firmware: reduce number of DAC initialization attempts
...
Faster startup when one DAC is broken.
2018-06-19 19:10:23 +08:00
Sebastien Bourdeauducq
1d594d0c97
firmware: make DAC initialization failures non-fatal
...
This allows using RTMs with one broken DAC for development.
2018-06-19 19:09:38 +08:00
Sebastien Bourdeauducq
158b5e3083
satman: program Allaki
2018-06-19 18:09:05 +08:00
Sebastien Bourdeauducq
574892a4e5
firmware/serwb: cleanup and improve messaging
2018-06-19 15:11:03 +08:00
Sebastien Bourdeauducq
c862471165
typo
2018-06-19 14:35:24 +08:00
Sebastien Bourdeauducq
433273dd95
sayma: support RTM FPGA, HMC830 and HMC7043 in DRTIO master and satellite
2018-06-19 14:33:48 +08:00
Sebastien Bourdeauducq
476cfa0f53
si5324: improve lock messaging
2018-06-19 14:29:57 +08:00
Sebastien Bourdeauducq
6403a0d5d1
sayma_amc: update without-sawg description
2018-06-19 13:52:05 +08:00
Sebastien Bourdeauducq
d29b3dd588
hmc830: compile-time configurable reference frequency
2018-06-19 13:47:32 +08:00
Sebastien Bourdeauducq
6f3ed81626
targets/sayma_rtm: fix description
2018-06-18 17:46:53 +08:00
Robert Jördens
21a48711ec
i2c: refactor common operations
2018-06-18 09:34:09 +00:00
Sebastien Bourdeauducq
0e640a6d6f
hmc7043: fix SYSREF to meet s/h at FPGA ( #794 )
2018-06-18 17:04:12 +08:00