forked from M-Labs/artiq
hmc7043: style
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@ -181,7 +181,6 @@ pub mod hmc7043 {
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(false, 0, 0x08), // 13: ADC1_SYSREF
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];
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fn spi_setup() {
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unsafe {
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while csr::converter_spi::idle_read() == 0 {}
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@ -279,25 +278,33 @@ pub mod hmc7043 {
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write(0x5c, (HMC_SYSREF_DIV & 0xff) as u8); // Set SYSREF timer divider
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write(0x5d, ((HMC_SYSREF_DIV & 0x0f) >> 8) as u8);
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for channel in 0..14 {
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for channel in 0..OUTPUT_CONFIG.len() {
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let channel_base = 0xc8 + 0x0a*(channel as u16);
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let (enabled, divider, outcfg) = OUTPUT_CONFIG[channel];
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if enabled {
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// Only clock channels need to be high-performance
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if (channel % 2) == 0 { write(channel_base, 0xd1); }
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else { write(channel_base, 0x51); }
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if channel % 2 == 0 {
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write(channel_base, 0xd1);
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} else {
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write(channel_base, 0x51);
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}
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} else {
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write(channel_base, 0x10);
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}
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else { write(channel_base, 0x10); }
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write(channel_base + 0x1, (divider & 0xff) as u8);
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write(channel_base + 0x2, ((divider & 0x0f) >> 8) as u8);
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// bypass analog phase shift on clock channels to reduce noise
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if (channel % 2) == 0 {
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if divider != 0 { write(channel_base + 0x7, 0x00); } // enable divider
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else { write(channel_base + 0x7, 0x03); } // bypass divider for lowest noise
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// bypass analog phase shift on DCLK channels to reduce noise
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if channel % 2 == 0 {
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if divider != 0 {
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write(channel_base + 0x7, 0x00); // enable divider
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} else {
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write(channel_base + 0x7, 0x03); // bypass divider for lowest noise
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}
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} else {
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write(channel_base + 0x7, 0x01);
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}
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else { write(channel_base + 0x7, 0x01); }
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write(channel_base + 0x8, outcfg)
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}
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@ -311,13 +318,13 @@ pub mod hmc7043 {
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}
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pub fn cfg_dac_sysref(dacno: u8, phase: u16) {
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spi_setup();
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/* Analog delay resolution: 25ps
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* Digital delay resolution: 1/2 input clock cycle = 416ps for 1.2GHz
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* 16*25ps = 400ps: limit analog delay to 16 steps instead of 32.
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*/
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let analog_delay = (phase % 17) as u8;
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let digital_delay = (phase / 17) as u8;
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spi_setup();
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if dacno == 0 {
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write(0x00d5, analog_delay);
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write(0x00d6, digital_delay);
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