forked from M-Labs/artiq
hmc7043: stricter check of FPGA SYSREF margin
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@ -374,11 +374,11 @@ pub mod hmc7043 {
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}
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info!(" ...done ({}/{} slips), verifying timing margin", slips0, slips1);
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let mut margin = None;
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let mut margin_plus = None;
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for d in 0..phase_offset {
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sysref_offset_fpga(phase_offset - d);
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if !sysref_sample() {
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margin = Some(d);
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margin_plus = Some(d);
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break;
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}
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}
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@ -386,10 +386,13 @@ pub mod hmc7043 {
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// meet setup/hold
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sysref_offset_fpga(phase_offset);
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if margin.is_some() {
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let margin = margin.unwrap();
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info!(" margin at FPGA: {}", margin);
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if margin < 10 {
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if margin_plus.is_some() {
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let margin_plus = margin_plus.unwrap();
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// one phase slip (period of the 1.2GHz input clock)
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let period = 2*17; // approximate: 2 digital coarse delay steps
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let margin_minus = if period > margin_plus { period - margin_plus } else { 0 };
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info!(" margin at FPGA: -{} +{}", margin_minus, margin_plus);
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if margin_minus < 10 || margin_plus < 10 {
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error!("SYSREF margin at FPGA is too small");
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}
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} else {
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