forked from M-Labs/artiq
drtio: resync SYSREF when TSC is loaded
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5a2a857a2f
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@ -56,6 +56,11 @@ mod moninj;
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#[cfg(has_rtio_analyzer)]
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mod analyzer;
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#[cfg(has_ad9154)]
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const SYSREF_PHASE_FPGA: u16 = 32;
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#[cfg(has_ad9154)]
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const SYSREF_PHASE_DAC: u16 = 61;
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fn startup() {
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irq::set_mask(0);
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irq::set_ie(true);
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@ -109,7 +114,7 @@ fn startup() {
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/* must be the first SPI init because of HMC830 SPI mode selection */
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board_artiq::hmc830_7043::init().expect("cannot initialize HMC830/7043");
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#[cfg(has_ad9154)]
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board_artiq::ad9154::init(44, 61);
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board_artiq::ad9154::init(SYSREF_PHASE_FPGA, SYSREF_PHASE_DAC);
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#[cfg(has_allaki_atts)]
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board_artiq::hmc542::program_all(8/*=4dB*/);
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@ -26,6 +26,16 @@ fn drtio_reset_phy(reset: bool) {
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}
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}
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fn drtio_tsc_loaded() -> bool {
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unsafe {
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let tsc_loaded = (csr::DRTIO[0].tsc_loaded_read)() == 1;
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if tsc_loaded {
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(csr::DRTIO[0].tsc_loaded_write)(1);
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}
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tsc_loaded
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}
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}
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fn process_aux_packet(packet: drtioaux::Packet) -> Result<(), drtioaux::Error<!>> {
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// In the code below, *_chan_sel_write takes an u8 if there are fewer than 256 channels,
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// and u16 otherwise; hence the `as _` conversion.
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@ -238,6 +248,12 @@ fn drtio_link_rx_up() -> bool {
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}
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}
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const SIPHASER_PHASE: u16 = 32;
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#[cfg(has_ad9154)]
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const SYSREF_PHASE_FPGA: u16 = 32;
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#[cfg(has_ad9154)]
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const SYSREF_PHASE_DAC: u16 = 61;
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#[no_mangle]
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pub extern fn main() -> i32 {
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clock::init();
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@ -262,7 +278,7 @@ pub extern fn main() -> i32 {
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/* must be the first SPI init because of HMC830 SPI mode selection */
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hmc830_7043::init().expect("cannot initialize HMC830/7043");
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#[cfg(has_ad9154)]
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board_artiq::ad9154::init(32, 61);
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board_artiq::ad9154::init(SYSREF_PHASE_FPGA, SYSREF_PHASE_DAC);
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#[cfg(has_allaki_atts)]
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board_artiq::hmc542::program_all(8/*=4dB*/);
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@ -272,16 +288,23 @@ pub extern fn main() -> i32 {
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}
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info!("link is up, switching to recovered clock");
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si5324::siphaser::select_recovered_clock(true).expect("failed to switch clocks");
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si5324::siphaser::calibrate_skew(32).expect("failed to calibrate skew");
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si5324::siphaser::calibrate_skew(SIPHASER_PHASE).expect("failed to calibrate skew");
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drtioaux::reset(0);
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drtio_reset(false);
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drtio_reset_phy(false);
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while drtio_link_rx_up() {
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process_errors();
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process_aux_packets();
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#[cfg(has_hmc830_7043)]
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{
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if drtio_tsc_loaded() {
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hmc830_7043::hmc7043::sysref_rtio_align(SYSREF_PHASE_FPGA);
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}
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}
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}
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drtio_reset_phy(true);
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drtio_reset(true);
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drtio_tsc_loaded();
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info!("link is down, switching to local crystal clock");
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si5324::siphaser::select_recovered_clock(false).expect("failed to switch clocks");
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}
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@ -2,6 +2,7 @@ from types import SimpleNamespace
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from migen import *
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from migen.genlib.resetsync import AsyncResetSynchronizer
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from migen.genlib.cdc import PulseSynchronizer
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from misoc.interconnect.csr import *
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from artiq.gateware.rtio.sed.core import *
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@ -34,6 +35,7 @@ class DRTIOSatellite(Module):
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lane_count=8, fifo_depth=128):
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self.reset = CSRStorage(reset=1)
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self.reset_phy = CSRStorage(reset=1)
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self.tsc_loaded = CSR()
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self.clock_domains.cd_rio = ClockDomain()
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self.clock_domains.cd_rio_phy = ClockDomain()
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@ -92,6 +94,14 @@ class DRTIOSatellite(Module):
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self.comb += self.rt_packet.cri.counter.eq(coarse_ts << fine_ts_width)
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self.coarse_ts = coarse_ts
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ps_tsc_load = PulseSynchronizer("rtio", "sys")
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self.submodules += ps_tsc_load
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self.comb += ps_tsc_load.i.eq(self.rt_packet.tsc_load)
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self.sync += [
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If(self.tsc_loaded.re, self.tsc_loaded.w.eq(0)),
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If(ps_tsc_load.o, self.tsc_loaded.w.eq(1))
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]
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self.submodules.outputs = ClockDomainsRenamer("rio")(
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SED(channels, fine_ts_width, "sync",
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lane_count=lane_count, fifo_depth=fifo_depth,
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@ -112,7 +122,7 @@ class DRTIOSatellite(Module):
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self.link_layer)
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def get_csrs(self):
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return ([self.reset, self.reset_phy] +
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return ([self.reset, self.reset_phy, self.tsc_loaded] +
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self.link_layer.get_csrs() + self.link_stats.get_csrs() +
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self.rt_errors.get_csrs() + self.aux_controller.get_csrs())
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