Commit Graph

8223 Commits

Author SHA1 Message Date
46604300a2 flake: update dependencies 2021-11-10 14:59:02 +08:00
c029977a27 flake: update dependencies 2021-11-10 09:54:34 +08:00
80115fcc02 flake: apply llvmlite callsite patch 2021-11-08 17:34:30 +08:00
ac2f55b3ff flake: patch llvmlite 2021-11-08 16:59:08 +08:00
db3e5e83e6 bump misoc 2021-11-08 16:59:08 +08:00
09945ecc4d gateware: fix drtio/dma tests 2021-11-08 16:59:08 +08:00
02119282b8 build_soc: build VexRiscv_G if not kasli v1.x 2021-11-08 16:59:08 +08:00
750b0ce46d ddb_temp: select appropriate compiler target 2021-11-08 16:59:08 +08:00
531670d6c5 dyld: check ABI 2021-11-08 16:59:08 +08:00
0f660735bf ll_gen: adjust csr address by detecting target class 2021-11-08 16:59:08 +08:00
0755757601 compiler/tb: use FPU 2021-11-08 16:59:08 +08:00
0d708cd61a compiler/target: split RISCV target into float/non-float 2021-11-08 16:59:08 +08:00
03b803e764 firmware: adjust csr separation 2021-11-08 16:59:08 +08:00
b3e315e24a rust: find json file using CARGO_TRIPLE 2021-11-08 16:59:08 +08:00
0898e101e2 board_misoc: reuse riscv dir for comm & kernel 2021-11-08 16:59:08 +08:00
cb247f235f gateware: pass adr_w/data_w to submodules 2021-11-08 16:59:08 +08:00
90f944481c kernel_cpu: add fpu if not kasli v1.x 2021-11-08 16:59:08 +08:00
d84ad0095b comm_cpu: select 64b bus if not kasli v1.x 2021-11-08 16:59:08 +08:00
dd68b4ab82 mailbox: parametrize address width 2021-11-08 16:59:08 +08:00
c6e0e26440 drtio: accept 32b/64b bus 2021-11-08 16:59:08 +08:00
8da924ec0f dma: set conversion granularity using bus width 2021-11-08 16:59:08 +08:00
591507a7c0
Merge pull request #1774 from m-labs/fastino-cic
Fastino cic
2021-10-28 17:44:20 +02:00
5a5b0cc7c0 fastino: expand docs 2021-10-28 15:19:48 +00:00
69cddc6b86
rtio_clocking: add warnings for unsupported rtio_clock settings (#1773) 2021-10-28 16:34:22 +08:00
9b1d7e297d
runtime: clock input specification improvements
closes #1735
2021-10-28 16:21:51 +08:00
21b07dc667 flake: fix missing freetype & fontconfig libs for Vivado GUI mode 2021-10-28 14:39:47 +08:00
1ff474893d Revert "fastino: make driver filter order configurable"
This reverts commit 10c37b87ec.
2021-10-28 06:29:56 +00:00
10c37b87ec fastino: make driver filter order configurable 2021-10-27 20:24:58 +00:00
c940f104f1 artiq_flash: fix gateware header not in little-endian for RISC-V 2021-10-25 11:20:26 +08:00
0aa8a739aa sayma_rtm: fix RTM firmware not in little-endian for RISC-V 2021-10-25 11:20:26 +08:00
43eab14f56 flake: update dependencies 2021-10-21 15:06:38 +08:00
cc15a4f572 flake: update Vivado 2021-10-21 11:24:55 +08:00
df6aeb99f6 flake: check gateware timing 2021-10-18 11:09:10 +08:00
bb61f2dae6 flake: update dependencies 2021-10-18 10:38:28 +08:00
b0cbad530b flake: update dependencies 2021-10-16 19:10:28 +08:00
92cdfac35a flake: fix cargoDeps sha256 2021-10-16 18:20:25 +08:00
bf180c168c flake.lock: update dependencies 2021-10-16 17:42:24 +08:00
d5fa3d131a cargo.lock: update libc version for libfringe 2021-10-16 17:42:24 +08:00
6d3164a912 riscv: print mtval on panic 2021-10-16 17:42:24 +08:00
46326716fd runtime: bump libfringe, impl ecall abi
See libfringe PR: M-Labs/libfringe#1
2021-10-16 17:42:24 +08:00
0a59c889de satman/kern: init locked PMP on startup 2021-10-16 17:42:24 +08:00
27a7a96626 runtime: setup pmp + transfer to user 2021-10-16 17:42:24 +08:00
a0bf11b465 riscv: impl pmp 2021-10-16 17:42:24 +08:00
790a20edf6 linker: generate stack guard + symbol 2021-10-16 17:42:24 +08:00
fanmingyu212
178a86bcda master: add an argument to set an experiment subdirectory
Signed-off-by: Mingyu Fan <mingyufan@ucsb.edu>
2021-10-15 16:54:31 +08:00
35d21c98d3 Revert "runtime: expose rint from libm"
Consistency with NAR3/Zynq where rint is not available.

This reverts commit f5100702f6.
2021-10-11 08:12:04 +08:00
f5100702f6 runtime: expose rint from libm 2021-10-10 20:40:17 +08:00
3c1cbf47d2 phaser: add more slack during init. Closes #1757 2021-10-10 16:18:55 +08:00
3f6bf33298 fastino: add interpolator support 2021-10-08 15:47:07 +00:00
501eb1fa23 flake: add microscope 2021-10-08 12:39:35 +08:00