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compiler/tb: use FPU

This commit is contained in:
occheung 2021-11-08 13:00:26 +08:00 committed by Sébastien Bourdeauducq
parent 0d708cd61a
commit 0755757601
3 changed files with 6 additions and 6 deletions

View File

@ -1,7 +1,7 @@
import sys, os
from pythonparser import diagnostic
from ..module import Module, Source
from ..targets import RISCVTarget
from ..targets import RV32GTarget
from . import benchmark
def main():
@ -30,7 +30,7 @@ def main():
benchmark(lambda: Module(source),
"ARTIQ transforms and validators")
benchmark(lambda: RISCVTarget().compile_and_link([module]),
benchmark(lambda: RV32GTarget().compile_and_link([module]),
"LLVM optimization and linking")
if __name__ == "__main__":

View File

@ -5,7 +5,7 @@ from ...master.databases import DeviceDB, DatasetDB
from ...master.worker_db import DeviceManager, DatasetManager
from ..module import Module
from ..embedding import Stitcher
from ..targets import RISCVTarget
from ..targets import RV32GTarget
from . import benchmark
@ -45,7 +45,7 @@ def main():
stitcher = embed()
module = Module(stitcher)
target = RISCVTarget()
target = RV32GTarget()
llvm_ir = target.compile(module)
elf_obj = target.assemble(llvm_ir)
elf_shlib = target.link([elf_obj])

View File

@ -1,7 +1,7 @@
import sys, os
from pythonparser import diagnostic
from ..module import Module, Source
from ..targets import RISCVTarget
from ..targets import RV32GTarget
def main():
if not len(sys.argv) > 1:
@ -20,7 +20,7 @@ def main():
for filename in sys.argv[1:]:
modules.append(Module(Source.from_filename(filename, engine=engine)))
llobj = RISCVTarget().compile_and_link(modules)
llobj = RV32GTarget().compile_and_link(modules)
basename, ext = os.path.splitext(sys.argv[-1])
with open(basename + ".so", "wb") as f: